How to generate IC style via cut arrays in GDS output?

As designs get more involved in WLP designs, there is a need to create IC style via cut arrays in Packaging tools.

I have created IC style via cut arrays in Allegro X Advanced Package Designer. How do I create a GDSII file from it?

For example, take the following cross-section:

RDL1  (conductor)

VIA1 (dielectric)

RDL2 (conductor)

Assume IC style via cut padstack(s) are correctly created (See the related article). You can now create a streamout file. You need to have a layer mapping file (.cnv) with the following entries:

##########################

72 10  CONDUCTOR RDL1

72 10  VIA_CLASS RDL1

##########################

4  1  VIA_CLASS VIA1

4  1  VIA_CONN  VIA1!RDL2

##########################

72 20  CONDUCTOR RDL2

72 20  VIA_CLASS RDL2

###############################

Then, you can have the IC style via cut arrays in GDS.

Here are the steps to export GDS file from APD/SiP:

Manufacture > Stream Out

• Provide GDS file name in the Output file name field.

• Provide top cell name in the Top structure name field.

• Browser the cnv file (which has the correct format mentioned above) for Layer conversion file.

• Click on the Export button.

  Then, you will have GDS with IC style via cut array as shown in the following image: