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Why do symmetrical etch layers show different impedance values in Display > Parasitic?

Electro Node

Hi everyone,

I routed clines on L4 and L5 with the same width, and both layers are symmetrical to the shield ground.

However, in Display > Parasitic, I’m seeing different impedance values. I expected them to be similar.

Has anyone seen this before?
Which stackup or cross-section setting should I check first? Could this be related to conductor properties in the field solver?

Thanks in advance!

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  • TechnoBobby
    0

    Hi  ,

    This is usually caused by an incorrect conductor dielectric constant setting. If it differs significantly from the surrounding dielectric, the field solver may report different impedance values even for symmetrical layers.

    Update it in Setup > Cross-section so it matches (or is close to) the surrounding dielectric value.

    Hope this helps!

  • BR202606212147
    0 in reply to TechnoBobby

    Have you checked whether copper roughness, etch factors, or layer-specific conductor properties differ between L4 and L5 in the field solver setup? Those settings can sometimes create unexpected impedance variations even in an apparently symmetrical structure.

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  • BR202606212147
    0 in reply to TechnoBobby

    Have you checked whether copper roughness, etch factors, or layer-specific conductor properties differ between L4 and L5 in the field solver setup? Those settings can sometimes create unexpected impedance variations even in an apparently symmetrical structure.

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