How to import a die component from DEF?

Cadence IC Package design tools support many formats for importing a die component for placement into your package substrate layout. For standard die components, this includes the Cadence OpenAccess format, industry-standard LEF/DEF, die text files, and D.I.E. format files. For co-design dies, this includes OpenAccess, LEF/DEF, and die abstract files.

While the die text file remains the most common method for importing a die into APD or SiP, LEF/DEF is a good alternative if you need to be able to generate DEF files back out of the package design for sending back to your IC designers if they do not support reading a die text file.

Note: The LEF/DEF flow requires that you have access to the LEF library information for the top-level I/O driver and cover bump macro cells. If you do not have all this information, you will not be able to import a die from DEF, as the DEF file contains only macro-placement data and not the information about the macros themselves. You do not need the LEF information for core cells.

We will discuss importing IC LEF library files for use with your package tools, importing a die design from a DEF file to create a standard die component, and updating your library files when you receive new versions from your IC design team or move to a new release of APD / SiP.
 

Procedure 1: Readying LEF Library Information for Use with Allegro X APD

Before you can import any DEF file to add it as a die in your package substrate, you must import the corresponding LEF library files.

Because APD and SiP only need the top metal cells like the cover bump and I/O driver macros (those cells containing pins that represent package-accessible die pads in the manufactured die part), these tools generate smaller files containing just the information relevant in the package. These files have a .cml file extension, which stands for Compressed Macro Library.

The Setup > LEF Libraries ("lef lib") command is used to specify a set of related LEF library files and to generate the corresponding CML files for each LEF file. Run this command, which brings up the interface as shown below.

First, specify the name and location of the Library Definition File (LDF). Typically, this will be located in the same directory as your LEF library files. If your LEF library files are stored in a central, shared location, consider creating the LDF file in that directory so that the same file can be accessed by all your designers.

Next, define a library name. Once your LDF file name is specified, the Add button for the library will be activated. Click this button and specify the name. The LDF file can contain multiple sets of LEF files, each one representing a different library of LEF files. In this flow, you will define a single library only. Repeat these steps to define additional libraries if you need to.

With the LDF and library specified, it is time to add all the LEF files that are needed for this type of design. The set of LEF files must include the IC technology information in the first LEF file in the list, followed by all the LEF files which define all the macro cell definitions which contain die pads. Add these files one at a time to the list using the Add button. The technology LEF file will automatically be moved to the top of the list when it is added, but it is up to you to order the remaining LEF files to match the order in which they are referenced in the IC design space. 

Once you have finished adding and ordering the LEF files for your library, click on the first LEF file in the list and notice that the status of the CML file is listed as "Does not exist", as shown in the previous image. You need to configure the LEF files to guide the system as to which macro pins represent die pads. This process is not as complicated as it sounds, and is mostly a matter of confirming settings.

Begin by selecting the LEF technology file, the first file in the list ("aio.lef" in this example) and click the Options button. This opens the form shown below, initially on the General page. Here, you need to identify the IC metal layer on which the die pads are located. Normally, this will be the highest metal layer in the technology information. Select the correct layer in the IC Layers grid and set the mapping to "die pin". Then, close this form by clicking OK and, on the main LEF Library form, click the Auto create button. This will generate a CML file for this LEF file; you will notice that the CML status changes to "Up to date" to reflect this.

Note: CML files are located in the same directory as the LEF file to which they belong. Therefore, you MUST have write access to this directory.

Next, for each remaining LEF file, select the file and click the Options button. On the Pins page, set the minimum die pin width and height fields (You may need to obtain these settings from your IC design team if you do not know what the correct values should be).

When you set the values, the list of pin names that will be considered as die pads automatically populates. If you see a pin name that you know should be globally excluded, change its setting in the grid at the bottom of the form. These fields are highlighted in the image below.

When you are happy with the settings, click OK, return to the main LEF Library command form, and again click the Auto create button. Repeat the process for all remaining LEF files.

Note: In the rare case where you have die pads that are smaller than the minimum die pin size filter (or internal connection points that are larger than the filter size), you can use the Macros tab of the Options form to manually adjust the pad type for these pins on the affected macro(s). These customizations will be recorded in the CML file; so, you will not need to enter them again for this file even when you receive a new version of the LEF library.

Procedure 2: Importing a Die Component from DEF

Once your IC library files have been imported and your CML files generated, importing a specific IC design to place a die component instance is very straightforward. Before beginning, ensure that your package substrate cross-section has been set up.

If your DEF file represents a wire bond die, be sure to add a DIESTACK type layer above the top substrate layer or below the bottom substrate layer, depending on which side of the package substrate the die will be mounted to.

With your cross-section defined, run the Add > Standard Die > DEF (Die Pins Only) ("def in") command. You will be presented with the main DEF Import form as shown below.

To import the design from DEF, first ensure that the correct IC library is active. This is shown at the top of the form. If the wrong library is active, change to the proper one using the Library Manager button to the right of the library name. Then, browse to the DEF file that contains your IC design.

Finally, configure the die type and placement information on the bottom portion of the form. Select the correct chip attachment type and orientation (typically, Wire bond Chip-up or Flip chip Chip-down for mounting on top of the package substrate). If this die will go through an optical shrink during fabrication, ensure you set the shrink and scribe values, as appropriate.

The pad layer and the X/Y location of the die origin are also set on this form. However, you can always move the die after initial creation, if you need to, by using the Edit > Move ("move") or Edit > Die Stack ("diestack editor") command. So, do not worry if you do not know the exact placement details or need to optimize the die positioning to optimize the routing on your package substrate.

Click the Import button when you are satisfied with all the information on the form. The die will be imported into the active drawing. You should verify the results to ensure that all your library settings are correct and that no die pads have been missed (and no internal IC pins have been incorrectly flagged as die pads).
 

Procedure 3: Updating Library Files when They Change or You Update to a New Version of Your Package Design Tool

When you receive new versions of LEF library files from your IC design team, you must refresh the CML files for those LEF files. Do this by running the Setup > LEF Libraries ("lef lib") tool. Browse to your library definition file if it is not already active, and select the library containing the LEF files to be refreshed.

For each LEF file which has been modified, the CML status will show "Out of date" as shown in the image below. Click the Auto create button to regenerate the CML file based on the new LEF file’s contents.

Since the CML file stores your settings from the Options page as well as the macro cell definitions, it is not necessary to open the Options tab prior to performing the update. Any customizations you have made will be preserved when the macros are processed and the new CML generated.

When you move to a newer release of your Cadence IC Package layout design tools, you should perform the same procedures listed above. This time, however, be sure to regenerate ALL CML files. The tool will not automatically refresh your CML files in order to ensure that. If you have multiple releases of APD / SiP installed, the files are not made incompatible with earlier releases of the tools that you are still using.