Stats

  • Replies 4
  • Subscribers 64
  • Views 7646
  • Members are here 0
More Content

From Virtuoso Layout to package & PCB

archive

Hello all,

I have a couple of newbie questions on the suggested design flow of the evaluation PCB for my chip design. I've done my chip design in Cadence Virtuoso, and sent it to the manufacturing house for tapeout and packaging. Now I would like to design a PCB for it in Cadence Allegro, and if possible simulate the whole IC-package-PCB system before manufacturing the PCB.

Packaging will be done for me, so far I can only get the physical characteristics of the package (type, dimensions, pin pitch etc), and I'm not sure that I will be able to obtain the details on how wire bonding was done. Therefore, I was thinking of exporting my IC data from Virtuoso, placing it inside a package I'd generate with Package Wizard, and doing simple autorouting.

1. For purposes of creating the package, how do I get my physical IC data into Allegro? Can I import it into the Package Designer, or do I need to go through Design Entry CIS, and which format to use?

2. For simulating the whole IC-package-PCB, can I use the netlist extracted by Mentor Graphics Calibre (includes all the parasitics)? What format should I extract the data into - HSPICE, Spectre or some other? What component of Allegro do I use for simulating (in Virtuoso I was using Analog Environment with Spectre or HSPICE models)?

Sorry for the long post - if there's some sort of a tutorial covering this flow, I'd appreciate info on where to find it. Thanks a lot in advance!

Pavle
University of Illinois


Originally posted in cdnusers.org by PavleM
Parents

  • The Allegro RFSIP product has the functionality to generate a die footprint and the die text file used in Packaging. Depending upon the type of IC (digital, Analog or Mixed) and data speeds would dictate the method of simulation and products used. Your comments about the packaging being taken care of and not being much of a factor is in my opinion far from reality. Packaging is just as important as the PCB and more so in terms of budgeting. Mainstream design flows comprehend co-design of the IC-PKG-PCB. Allegro has this functionality as well.

    Best Regards,
    Dan


    Originally posted in cdnusers.org by dbaldwin
Reply

  • The Allegro RFSIP product has the functionality to generate a die footprint and the die text file used in Packaging. Depending upon the type of IC (digital, Analog or Mixed) and data speeds would dictate the method of simulation and products used. Your comments about the packaging being taken care of and not being much of a factor is in my opinion far from reality. Packaging is just as important as the PCB and more so in terms of budgeting. Mainstream design flows comprehend co-design of the IC-PKG-PCB. Allegro has this functionality as well.

    Best Regards,
    Dan


    Originally posted in cdnusers.org by dbaldwin
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.