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  2. Allegro X Capture CIS
  3. Capture - Net name from port name

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Capture - Net name from port name

Fredda
Fredda over 5 years ago

Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.

/F

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  • Fredda
    0 Fredda over 5 years ago

    Ok, it seems like a net will get the same name as the port name. The problem is one step up in the hierarchy. A net that connects to pin on a hierarchical block will not get the net name of the underlying port in spite of being the same net.

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  • UlfK
    0 UlfK over 5 years ago in reply to Fredda

    And this is an "Ouch" since it is not transferred to layout. In case you have a netname indicating need for fat traces, it will not be carried over to the PCB Editor...

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  • Fredda
    0 Fredda over 5 years ago in reply to UlfK

    Exactly. And that was my main issue.

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  • oldmouldy
    0 oldmouldy over 5 years ago in reply to Fredda

    Net naming has to work "Top Down" through a hierarchy, otherwise it would be impossible to support a complex hierarchy, multiple hierarchical blocks that reference the same underlying schematic. The Net properties get derived from all of the properties that are assigned to the placed Wires in the Schematic and result in a "Flat Net", which is transferred to the PCB, and associated properties. Select the DSN file entry and use Edit>Object Properties and select the Flat Nets tab to see what properties are attached.

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