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Setting up a bussed differential pair (DDR CLK)

Can anyone tell me how to properly define a bussed differential pair so the static phase can be tuned for each individual segment?

The DDR CLK pair runs from FPGA thru five DDR components. After routing the CLK pair, constraint manager automatically defines some random set of pin pairs.

I cannot create pin pairs or delete any of these pairs.

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0 TSCphil over 5 years ago

FYI - running 17.2 with hotfix 63
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0 TSCphil over 5 years ago

FYI - running 17.2 with hotfix 63
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0 steve over 5 years ago in reply to TSCphil

So Static Phase is a one time check from driver to reciever (the complete net). Dynamic Phase looks at length and tolerance. Pin Pairs are limited to Relative Propagation Delay and Min/Max Propagation delay worksheets. For what you want to do you may be better to create a matched group for the diff pairs.
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