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Setting up a bussed differential pair (DDR CLK)

TSCphil

Can anyone tell me how to properly define a bussed differential pair so the static phase can be tuned for each individual segment?

The DDR CLK pair runs from FPGA thru five DDR components. After routing the CLK pair, constraint manager automatically defines some random set of pin pairs.

I cannot create pin pairs or delete any of these pairs.

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    Steve, I do have a relative propagation delay match group for each section of the bussed diffpair. i.e FPGA to DDR1, DDR1 to DDR2, DDR2 to DDR3 and so on.

    That's not the problem. Tuning the static phase for each diffpair section has to be done first before you can tune the prop delay for each match group. But the static phase can not be defined by pin pairs.

    As it turns out, each diffpair section is the target trace for each prop delay group.

    I did figure out a work around though. I routed each section of the diffpair and tuned the static phase for each section, one at a time....before routing the section from FPGA to DDR1.

    Static phase tune is now resolved for each section of the diffpair.

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  • 0

    Steve, I do have a relative propagation delay match group for each section of the bussed diffpair. i.e FPGA to DDR1, DDR1 to DDR2, DDR2 to DDR3 and so on.

    That's not the problem. Tuning the static phase for each diffpair section has to be done first before you can tune the prop delay for each match group. But the static phase can not be defined by pin pairs.

    As it turns out, each diffpair section is the target trace for each prop delay group.

    I did figure out a work around though. I routed each section of the diffpair and tuned the static phase for each section, one at a time....before routing the section from FPGA to DDR1.

    Static phase tune is now resolved for each section of the diffpair.

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