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DRC v ERC on OrCAD 17.4

RWEV

Folks,

I am richly experienced in schematic design, worked on a lot of a different CAD systems, so am not at all new to this, but am new to Windows based OrCAD (used the DOS based one many moons ago). 

Am working on OrCAD 17,4 and would like clarification about what I would normally call ERC, but might be called DRC here, it's not clear to me.

In, I thnk, every other CAD system I've used I'd do an ERC - engineering rules check - on the schematic and a DRC - design rulex check on the PCB. Here, OrCAD seems to have a DRC and after running it, it's put green circles absolutely all over the place in irrelevant spots with liberal use of "Same pin number connected to multiple nets". So, I have some questions:

1. Is it really a DRC that is used where other CAD systems would use ERC?

2. How do I rid myself of these green markers? I found a video on line for an older version of OrCAD, but the menus have changed orr this version.

3. If DRC really is ERC, how do I turn off unwanted checks like "Same pin number connected to multiple nets"?

Thanks!  I'm sure there'll be more questions on this once I've worked out those questions.

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    OrCAD Capture has always referred to "checking the design" as DRC. There is an ERC matrix which configures checking Pin Type to Pin Type.

    If you have "Same Pin Number connected to multiple Nets", you probably need to check that the design is annotated correctly since this is really reporting "same pin number and the same RefDes connected to multiple nets" in most cases.

    "What" gets checked is configured from PCB>Design Rules Check, Rules Setup.

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  • 0

    OrCAD Capture has always referred to "checking the design" as DRC. There is an ERC matrix which configures checking Pin Type to Pin Type.

    If you have "Same Pin Number connected to multiple Nets", you probably need to check that the design is annotated correctly since this is really reporting "same pin number and the same RefDes connected to multiple nets" in most cases.

    "What" gets checked is configured from PCB>Design Rules Check, Rules Setup.

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