• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X Capture CIS
  3. Unable to generate netlist due to a part missing pin er...

Stats

  • State Not Answered
  • Replies 3
  • Subscribers 44
  • Views 7729
  • Members are here 0
More Content

Unable to generate netlist due to a part missing pin error

Neil mustafa
Neil mustafa over 2 years ago

Hi, 

I am trying to make modifications to my schematic and the board I already designed for it. So, I haven't made any changes yet but for some reason I cannot generate a netlist for the current schematic. This is what I get:

------ Oversights/Warnings/Errors ------


#1 ERROR(SPMHNI-191): Device/Symbol check error detected.

ERROR(SPMHNI-195): Symbol 'SOT89' for device 'MOSFET_N_GDSD_SOT89_TN2510N8-G' is missing pin '4'.

------ Library Paths ------
MODULEPATH = .
C:/Cadence/company/pcb/modules

PSMPATH = .
symbols
padstacks
C:\Cadence\company\pcb\padstacks
C:\Cadence\company\pcb\padstacks\student
C:\Cadence\company\pcb\padstacks\smartstart
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU_HOLE
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU_HOLE

PADPATH = .
symbols
padstacks
C:\Cadence\company\pcb\padstacks
C:\Cadence\company\pcb\padstacks\student
C:\Cadence\company\pcb\padstacks\smartstart
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU_HOLE


------ Summary Statistics ------


#2 Run stopped because errors were detected

netrev run on Sep 27 12:32:58 2022
DESIGN NAME : '0207501_SCH'
PACKAGING ON Mar 2 2016 00:37:24

COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF

FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON

2 errors detected
No oversight detected
No warning detected

cpu time 0:01:20
elapsed time 0:00:01

INFO(ORCAP-32005): *** Done ***

Now, looking at the part in question, it does indeed have 4 pins, so I am not sure what they mean by Pin 4 is "missing" or how to fix that.

Here is the Symbol the software is complaining about:

Here is the schematic that includes this part , with REF DES Q7

If there is anything else you need please let me know, your help is highly appreciated!

  • Sign in to reply
  • Cancel
  • oldmouldy
    0 oldmouldy over 2 years ago

    Quite likely, the SOT89 footprint has 3 pins (1,2,3) and you are trying to map a 4 pin Schematic Part to it. You will need to use a Footprint with 4 pins (1,2,3,4) for this to work.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • Neil mustafa
    0 Neil mustafa over 2 years ago in reply to oldmouldy

    Here is the SOT89.DRA file that is on my system. From what I am seeing it has 4 pads. Any thoughts of what else could be causing this? 
    All the parts that are in this schematic are database parts just like the one in question above.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • oldmouldy
    0 oldmouldy over 2 years ago in reply to Neil mustafa

    There is a SOT89 in the Cadence provided libraries that is a 3-pin part. Check that the padpath and psmpath User Preferences have your library folders above the provided library folders. (The folder search order is also listed in the netrev.lst file which is usually in the same folder as the board file)

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information