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Community PCB Design & IC Packaging (Allegro X) Allegro X Capture CIS Resolve roadblock in schematic design

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Resolve roadblock in schematic design

PCBTech
PCBTech 25 days ago

You’re working on a OrCAD Capture CIS design and when generating the netlist, you hit this roadblock:

 

ERROR (ORCAP-36022): Pin number missing from part ‘U3’
The symbol for U3 displays all its pins, visually I see all the pin numbers for part U3 still I get ERROR.
⸻
Question: What are the MOST LIKELY root causes for this error, and how should this be fixed?

 

 

A. Few pins were visually not represented — edit the symbol in the Part Editor, make sure all pins are set to visible and unique pin numbers are added.
B. Regenerate the netlist after restarting Capture to force a clean build.
C. Delete and replace existing part with the other part.

Share Insights !!

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  • Minet
    0 Minet 23 days ago

    I've not encountered this roadblock but I would double-check the part definition --- maybe the visible pin number is defined as a text element and not a property of the pin itself. Also check for duplicates.

    Do you still get the same error after performing the steps A, B and C?

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  • PCBTech
    0 PCBTech 14 days ago in reply to Minet

    Hi Minet,

    Sure do give a check.

    Step A helped in my schematic design.

    Have you used invisible pins in your design/part creation?

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  • Minet
    0 Minet 8 days ago in reply to PCBTech

    No we don't use invisible pins.

    I've had problems where the pin numbers were duplicated (this was a large BGA package) but the error message in Capture was quite clear about how to resolve it.

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  • PCBTech
    0 PCBTech 8 days ago in reply to Minet

    Thank you for sharing your experience.

    By removing duplicates from the design, you were able to successfully implement the large BGA package. We can check for duplicates as well based upon the info in Error message.

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