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PSpice only schematic symbol pins

kevcon

I there a way to create a schematic symbol that has extra pins for PSpice simulation but do not get mapped to a PCB footprint?

I cannot seem to make the netlist generator ignore the extra pins when I try to transfer the design to the pcb.

I am trying to avoid creating two separate schematic symbols.

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  • rg13
    0

    PSpiceOnly set to true OR NETLIST_IGNORE properties can be used to restrict any part going into netlist depending on your requirement. You can refer following link for more details:

    (+) Capture to Allegro: How to exclude a component from transfer to PCB - Allegro X Capture CIS - PCB Design & IC Packaging (Allegro X) - Cadence Community

    Also, there does not seem to be any way to ignore PSpice specific pins. Along with this, in general if we don't want to map extra logical pins to footprint, then we mark them as No connect (NC) but this way it won't be simulated in PSpice. creating 2 parts seems to be feasible option in this case.

  • kevcon
    0 in reply to rg13

    Hi rg13,

    After a bunch more testing I ended up making two separate footprints, it's a bit cumbersome but using the Testbench functionality in Capture makes it a bit easier.

    Kevin

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  • kevcon
    0 in reply to rg13

    Hi rg13,

    After a bunch more testing I ended up making two separate footprints, it's a bit cumbersome but using the Testbench functionality in Capture makes it a bit easier.

    Kevin

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