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Hetrgenous hierarchical blocks.

SolderMonkey

Hi all,

Pretty sure I know the answer to this one. But I'll ask anyway as there are lots of clever users out there...

Is there any means of using hetrogenous hierarchical blocks with Orcad Capture 17.4?

I have several big ASICs, each with many interfaces, the ASICs have hetrogenous schematic symbols as you'd expect. One schematic symbol for the PCIe, one for the ethernet etc.

The ASICs each live in their own hirarchical block and these blocks are hooked together with a top level schematic. The heirarachical block symbol at the top level are homogenous, one block with all the interfaces from the ASIC within. This makes for a very busy top level schematic.

If would be far nicer to have hetrogenous heirachical block symbols. Multiple symbols calling up one hierarchical schematic. That way at the top level we could have one page for the PCIe connectivity, one for the ethernet, one for the I2C etc. etc.

I've tried quite a few times to find a way to do this. So far I've failed. Does anyone know how to make it work please?

Parents
  • oldmouldy
    0

    No, there aren't any heterogeneous hierarchical blocks but what you can do is, for example, place each section of the ASIC on its own Page and make an H_Block from that. Then you can have a block that is just a specific section, or sections, of the ASIC and then connect those blocks together at a higher level in the design.

Reply
  • oldmouldy
    0

    No, there aren't any heterogeneous hierarchical blocks but what you can do is, for example, place each section of the ASIC on its own Page and make an H_Block from that. Then you can have a block that is just a specific section, or sections, of the ASIC and then connect those blocks together at a higher level in the design.

Children
  • SolderMonkey
    0 in reply to oldmouldy

    Thank you. That's a very interesting thought...

    I've been mulling it over and I don't think I can make it work for us. I've put in place a design methodology where each of the big ASIC blocks lives in it's own project. They all have their own .DSN and .OPJ files. The H-blocks in the top level schem point to the DSN of the sub-project.

    This gives us the ability for multiple engineers to work on the project at any one time, with each engineer working in a separate sub-project. It also makes for fast and easy design changes. I can swap out an ASIC in a sub-project with another design in a matter of minutes, without losing the original design. Finally it gives us really quick and easy design re-use and change control. We don't need to review the entire schem if we can be certain that only one to two sub-projects have changed.

    Whilst what you suggest is a really novel idea, I'd have to bin the sub-project approach to make it work and I don't think the benefits come close to making it worth losing all that sub-projects give us.

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