• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X Capture CIS
  3. Orcad 22 netlist gives errant rat in Allegro

Stats

  • State Not Answered
  • Replies 2
  • Subscribers 49
  • Views 478
  • Members are here 0
More Content

Orcad 22 netlist gives errant rat in Allegro

bustercrabby
bustercrabby 2 months ago

This has never happened before so I'm confused.

I have two symbols in my schematic that each have a pin called PAD. Both are 'Power' pins. Both have no connects attached and show up as 'Is No Connect' in the pin properties window.

After recreating the netlist and importing it into Allegro, there is a rat showing a connection between the two pins that are not supposed to be connected. Any thoughts on why this is happening? I think it is on the Orcad Netlist side as opposed to the Allegro side.

Thanks for any help you can give,

bustercrabby

  • Cancel
  • Sign in to reply
Parents
  • Zhifeng Jin
    0 Zhifeng Jin 1 month ago

    Five years ago, I encountered the exact same issue while reviewing TI’s DLP reference designs.
    The root cause was that the NC pins of two components were defined with the Power pin property.
    Even though there were no visible connections drawn in the schematic, Cadence automatically tied these pins together under a shared NC power net, simply because they had identical pin names and the Power attribute was enabled.

    This hidden connection is nearly impossible to spot visually in the schematic.
    However, once the netlist was imported into Allegro PCB Editor, the unintended electrical connection became obvious.
    It is extremely difficult to troubleshoot this kind of short circuit, especially for components with high pin counts. 

    It is recommended that when designing component symbols, the power pin property should never be assigned to non-power pins. Due to OrCAD's legacy design mechanism, any pins sharing the same name with the power attribute enabled will be internally connected by the software in the background, even without any wiring in the schematic.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Reply
  • Zhifeng Jin
    0 Zhifeng Jin 1 month ago

    Five years ago, I encountered the exact same issue while reviewing TI’s DLP reference designs.
    The root cause was that the NC pins of two components were defined with the Power pin property.
    Even though there were no visible connections drawn in the schematic, Cadence automatically tied these pins together under a shared NC power net, simply because they had identical pin names and the Power attribute was enabled.

    This hidden connection is nearly impossible to spot visually in the schematic.
    However, once the netlist was imported into Allegro PCB Editor, the unintended electrical connection became obvious.
    It is extremely difficult to troubleshoot this kind of short circuit, especially for components with high pin counts. 

    It is recommended that when designing component symbols, the power pin property should never be assigned to non-power pins. Due to OrCAD's legacy design mechanism, any pins sharing the same name with the power attribute enabled will be internally connected by the software in the background, even without any wiring in the schematic.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information