allegro import logic error

Hi,I'm new to the Allegro PCB Editor.I met a strange question need your help.

The question is "Before I have finished the design and created Artwork. I found a error in the design today,so I turn back to modify schematic which only added two resistance in two Nets and created PCB Editor netlist succesfully. But when I import to PCB Editor a pop-up window appeared which as shown in below Msg1.  And the Import Logic Viewlog have error information which show in below Msg2"

Msg1: pop-up error window information:  Program has encountered a problem and must exit. The design will be saved as a .SAV file that can be recovered using dbdoctor (if applicable). To resolve problem, first obtain the latest software updata from cadence and if the problem persists cantact cadence customer support. In additioon to the data cadence support request: please provide the MiniDump files found in folder"D:/CadenceWork/FPGA_OMAP_NEW/allegro".

Msg2: Veiwlog informatioon:

(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : NEW_FPGA_backup.brd                           )
(    Software Version : 16.6P004                                      )
(    Date/Time        : Mon Feb 24 17:12:49 2014                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY '.';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:/CadenceWork/FPGA_OMAP_NEW/allegro/NEW_FPGA_backup.brd';
NEW_BOARD_NAME 'D:/CadenceWork/FPGA_OMAP_NEW/allegro/NEW_FPGA_backup.brd';

CmdLine: netrev -$ -i . -y 1 -z D:/CadenceWork/FPGA_OMAP_NEW/allegro/#Taaaaaz02560.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.10)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.04)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.04)

------ Oversights/Warnings/Errors ------


#1   Run stopped because errors were detected

netrev run on Feb 24 17:12:49 2014
   DESIGN NAME : 'FPGA_DATA'
   PACKAGING ON Sep 10 2012 04:46:09

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  1 errors detected
 No oversight detected
 No warning detected

cpu time      0:05:45
elapsed time  0:00:03