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Package to Package spacing

Lennie

My footprint's are created so the part outline is created on the PLACE_BOUND layer. We create this so the correct outline is used for  IDF file generation.

This layer is also used by the package to package DRC. I have not found a way to change the preset value from "0" package to package clearance. Since this places the footprints next to each other  then we cannot build the

board. Is there any way around that ?

  • in reply to gdefond

    I do have to review and change every footprint import regardless of the source.   EDABuilder, a Cadence footprint builder, leaves you with an 0.1" grid spacing every damn time and do not try to put the DFA family property in or make the DFA boundary shape match the package size for 16.6. 

    My mechanical engineers can change connectors and pushbutton switch MPNs several times a day.  I send the MPN and manufacturer to PCBLibraryExpert.  Next day service if they don't have it.  Put an end to Engineers asking for tweaks to footprints based on gut feelings divided by the time span leading to my next vacation request.   Tom's PCBLibraryExpert library is the reason I don't have blood shooting out of my ears.  

    IPC-7351C incorporates component height with solder pad dimension calcs for chip passives. 

    https://idoc.pub/documents/what-is-new-in-ipc-7351c-d47755g2dj42

    It's easy for me to defend 7351C.  

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