Best practices for thermal pads with vias

Thank you!

I suppose you are using 16.6? I found images and videos of this interface and it all seems to be from 16.6 because I'm using 17.2 and the tool which seems to perform the same function is named differently and looks different. Or maybe it's just me? (I've used Allegro as an engineer for 10+ years but not to design pads, so while I know what I want to achieve making the padstack tool bend to my will is new to me.)

I was able to make a working padstack, spurred by your great details above, so let me write down what I did and hopefully if there are more people willing to chip in they can point out what I've done wrong or could do better. For the inquiring minds, I'm making the thermal pad shown on page 197 of https://www.analog.com/media/en/technical-documentation/data-sheets/adau1462-1466.pdf.

Naturally, we will begin on the Start tab. The padstack type must be "Thru Pin" to get copper on multiple etch layers. Using "SMD Pin" works to make a pad, but I want copper on internal and the bottom layer. (You will see a completed pad in the left panes, which will differ from what you will see as the padstack is being created.)

Moving to the Drill tab, we can then create the thermal vias. Select the hole type and diameter, then define the via pattern.

Note: A thermal pad 5.3mm on a side, with 7 vias along that side, should have vias spaced every ~0.88mm. Naturally, we need to shrink this a bit so all 7 vias are actually inside the pad. With 0.3mm vias, a 0.8mm via grid should work because the outsides of the vias in the row will be 5.15mm (0.8mm * 6 + 0.3mm). However, this doesn't work out and I had to select a 0.5mm via pattern grid to fit all the vias inside the thermal pad. I may be doing something wrong but there is a problem here. See below for more info.

I did not need the Secondary Drill tab, but do fill in the Drill Symbol tab. The Drill Offset tab pushes the entire via pattern around as you mentioned above. Not needed for me, but a cool trick. Thanks!

Create the copper pad shape on all layers according to your particular needs on the Design Layers and Mask Layers tabs. Check any desired settings in the Options tab.

Now we can add the padstack to a footprint:

Let's revisit the via grid issue mentioned above. The footprint grid is set to 0.5mm so we would expect each via to line up on a grid point. Hopefully this screenshot works out, but you can clearly see white dots of the grid points and they DO NOT line up with the vias. The first set of vias are just a bit past the middle of the grid points, which would be a just a bit over a 0.75mm grid. Perhaps I'm not interpreting something correctly but I don't see why the units aren't millimeter for the via pattern in the Padstack Editor. Definitely an issue somewhere.

Back to the footprint. I can then add rectangular pads on the mask layer with rounded corners to avoid the vias. The pad size is to give ~70% paste coverage (0.74mm^2 * 6 * 6 / 5.3mm^2 = ~0.7).

Unfortunately I don't know of a way to array a shape, so I make one and then copied it to form a row, then copied the row to fill out all columns. To place the shape I make one and dropped it down, then moved it with a user pick on the shape center.

Edit: Now is a good time to set the property DYN_THERMAL_CON_TYPE = FULL_CONTACT on the thermal pad so it directly connects to etch shapes on the PCB.

The last thing is to place the footprint and then check it out. All layers (notice the purple pastemask squares):

Just the top etch:

Just an inner etch layer:

Edit2: If a Gerber drill layer is desirable, make sure to check "Draw holes only" for the film since the "Thru Pin" will otherwise come out as a huge square hole.

This looks like a workable solution. But... is this the best way to make a footprint with thermal vias?

Found a problem. Because the thermal pad above is a Thru Pin type, that means it won't fall into the expected section of the Spacing domain in CM. As there is no THT part at this location it should adhere to a shape/cline constraint, but SMD pin would work I suppose.

We use selective solder pallets for double-sided boards and the footprint design above is a problem since this solder pallet needs relatively large spacing between SMD and THT pads on the side fitting into the pallet (typically the bottom side) so the solder wave can make it to THT pads. With the pad design above, Allegro thinks this pad is a THT pad forcing excessive spacing to meet the constraints or waiving a DRC error for inadequate spacing.

Does that make sense or have I written it confusingly? Any ideas how to resolve this issue?

Hi Evan, that is a nice write up you did, looks good. I am unsure about the CM errors you get but certainly CM can be massaged to give one the results they are after. If that bonding pad is an issue on the bottom layer just soldermask over it so in your footprint don't define a SM for the bottom pad. If you do that consider leaving the drill holes open, that is don't mask over the holes. 

Couple of thoughts. I think your web width for your solder paste is to fine it looks that way from the pictures. Normally a solder paste is done so the consideration is to allow for compression of the paste once the part is placed. Assuming they can create a stencil that fine because the web width is small "Distance between paste blobs" it is not going to control very well the spread of the paste when the part is placed.. Maybe less is more if that makes any sense.

I don't know what part you are using but they may have a note on the paste application. The drill holes around the outside of the pad look too close to the edge to me, again that could be just the picture, maybe consider having them further in from the pad edge. The name of the game on these pads is to get the heat off the dice. In your particular application there is plenty of room under the package for additional copper. By the looks of it you could make that bonding pad bigger than what the app note calls out for but keep the solder mask the same size as the bonding pad. Alot really depends on the thermals and the expected heat dissipation.

In Allegro/Orcad I have found the above mentioned method the best for doing those pads that act as a thermal escape for the dice on the package. You could do vias instead or a zero size padstack with just a drill hole. In those cases your back to dealing with pins and pins mean nets that have to be tied in. That extra baggage IMHO is just a pain. Other things like if you decide to move the part then your moving vias too, another total pain.

One last word of caution, check the data sheet. They may need heavier copper such as 2 oz on certain parts... It is kind of easy to miss that..

All the best.

excellon1

Thanks!

Managing the CM errors for vias placed inside the thermal pad aren't too bad and I already contacted Cadence about this and submitted a case. Hopefully an enhancement can be made.

The paste is just a quick example and it's not using actual design rules I implement for manufacturing. Thanks for clarifying that.

I still haven't implemented the above in any production footprints because of the thermal pad pin type. Thru Pin means I get the bogus clearance issues on the bottom side because of the selective solder pallet. I don't know how to resolve that in a way that isn't painful for users. And if the thermal pad is SMD Pin type, then I can only put copper on a single layer (Top or Bottom). That doesn't work because I need both of those (and possibly inner layers too). So IMO there's still a major problem that means this doesn't work. If you have some ideas to get around this issue that would be great.

Thanks for adding this. I have been doing layouts for years but new to Allegro, library type work. This was very helpful.