Creepage and clearance

I’ve struggled with this topic. Aren’t Spacing Rules in Allegro effectively creepage rules? They define object spacing on the PCB surfaces. I recognize there are some limitations: i.e. - it's not able to recognize slots or barriers in the calculation (as far as I know), but these would only increase the actual creepage distance, so you should be able to perform a robust verification leaving very little, if any, for manual verification, right?  Keeping in mind that the actual creepage value will always be equal or greater than the defined rule, you should be able to meet your creepage requirements using class-to-class Spacing rules.  What I’m I missing?

There are different levels of requirement based on metal to metal over solder mask and metal to metal under soldermask.  There are also pollution classes that need to be looked at.  Also you should verify the vendors ratings in the UL White pages.  This is not a trivial matter. 

The IPC rules using the Saturn tools shows spacing requirements for altitude - bare copper - solder resist and conform coating.

Understood. So use the appropriate value that corresponds to the requirement you choose. The question is: do the class-to-class and other Spacing Rules in Allegro serve to verify the creepage requirement. It seems to me they do. Again, unless I'm missing something.  

Understood. So use the appropriate value that corresponds to the requirement you choose. The question is: do the class-to-class and other Spacing Rules in Allegro serve to verify the creepage requirement. It seems to me they do. Again, unless I'm missing something.  

So far that's what we trying to use. But maybe we are familiar enough with the default constraint manager.

But maybe we are not familiar enough with the default constraint manager.

Hi Vinhl, Yeah, constraint management is an essential part of Allegro (or any PCB design tool). I'm sure there's plenty of CM material and/or videos on the Cadence Support site. Best regards.  

a follow up to this conversation ... so far the default constraint manager and Allegro can NOT manage/handle the creepage rule.

For example: the pin to pin distance must 10mm but due to board space we can only achieve 8mm. We add a slot between the 2 pins, the "creepage distance" is now 12mm (shortest distance measured from pin to slot to pin). However the DRC is still present because CM does not know that we have the slot.

We could manipulate the value in CM or create a constraint region but those options will not give us the true violation anymore. We could also waive the DRC (this is what we've been doing).

It would be nice if Cadence can somehow add a feature for creepage. We know of 1 software that could analyze the creepage and clearance but due to the current situation we don't have the budget to acquire said software.

Same here: we add cutouts on pvb so real crepage is o, and  "manage" it with commented waived DRC. I try using constraint area but it is for me dangerous: it cna hide a real problem. Waived DRC WITH comment and the name of person jusifying is much better for me.(example of problem with constraint area (already seen on a project, so....): constraint area larger than needed and/oir copied elsewhere where not applicable.)

Until real native mangement, waived DRC will be the only way for us.