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Creepage and clearance

vinhl

Hello,

Does anyone have any suggestions on a work-around about implementing creepage rule into a high voltage design?

I looked at the previous entry (over 14 years ago). It was not very explicit. I was hoping someone may have a better suggestion today.

We use allegro and OrCad.

There is a company in Germany that has a "plug-in" of some sort (NEXTRA). It states it is compatible with Cadence. We are looking at it as well. But was hoping we can do without it.

Thanks in advance.

Vinh.

  • in reply to LouShay

    a follow up to this conversation ... so far the default constraint manager and Allegro can NOT manage/handle the creepage rule.

    For example: the pin to pin distance must 10mm but due to board space we can only achieve 8mm. We add a slot between the 2 pins, the "creepage distance" is now 12mm (shortest distance measured from pin to slot to pin). However the DRC is still present because CM does not know that we have the slot.

    We could manipulate the value in CM or create a constraint region but those options will not give us the true violation anymore. We could also waive the DRC (this is what we've been doing).

    It would be nice if Cadence can somehow add a feature for creepage. We know of 1 software that could analyze the creepage and clearance but due to the current situation we don't have the budget to acquire said software.

  • in reply to vinhl

    Same here: we add cutouts on pvb so real crepage is o, and  "manage" it with commented waived DRC. I try using constraint area but it is for me dangerous: it cna hide a real problem. Waived DRC WITH comment and the name of person jusifying is much better for me.(example of problem with constraint area (already seen on a project, so....): constraint area larger than needed and/oir copied elsewhere where not applicable.)

    Until real native mangement, waived DRC will be the only way for us.

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