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Creepage and clearance

Hello,

Does anyone have any suggestions on a work-around about implementing creepage rule into a high voltage design?

I looked at the previous entry (over 14 years ago). It was not very explicit. I was hoping someone may have a better suggestion today.

We use allegro and OrCad.

There is a company in Germany that has a "plug-in" of some sort (NEXTRA). It states it is compatible with Cadence. We are looking at it as well. But was hoping we can do without it.

Thanks in advance.

Vinh.

Wild over 6 years ago in reply to LouShay

There are different levels of requirement based on metal to metal over solder mask and metal to metal under soldermask. There are also pollution classes that need to be looked at. Also you should verify the vendors ratings in the UL White pages. This is not a trivial matter.

The IPC rules using the Saturn tools shows spacing requirements for altitude - bare copper - solder resist and conform coating.
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LouShay over 6 years ago in reply to Wild

Understood. So use the appropriate value that corresponds to the requirement you choose. The question is: do the class-to-class and other Spacing Rules in Allegro serve to verify the creepage requirement. It seems to me they do. Again, unless I'm missing something.
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vinhl over 6 years ago in reply to LouShay

So far that's what we trying to use. But maybe we are familiar enough with the default constraint manager.
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vinhl over 6 years ago in reply to vinhl

But maybe we are not familiar enough with the default constraint manager.
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LouShay over 6 years ago in reply to vinhl

Hi Vinhl, Yeah, constraint management is an essential part of Allegro (or any PCB design tool). I'm sure there's plenty of CM material and/or videos on the Cadence Support site. Best regards.
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