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Regarding making layout from netlist

I have designed a schematic in allegro_design_entry_HDL.

I want to make its layout. But not able to do it, as i am not able to find the option for generating netlist . As per tutuorials it is said to have option of netlist at of Tools > Options > Creste nestlist , but i am not able to get it. And in allegro PCB designer i am not getting any options foe importing netlist. So what should i do .I am not able to proceed Its urgent. I am using allegro 17.2 linux version ? Is ithere any alternative of making layout irrespective of netlist?

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