Stats

  • Replies 17
  • Subscribers 161
  • Views 19903
  • Members are here 0
More Content

GND and VCC planes not assigned to GND VCC Nets

Cailloux

Schematic NETLIST is generated without any error. I can Import into PCB Editor from Import > Logic with no error. On my Schematic I have a GND Net and a VCC Net as well as many other Nets. The Cross Section is comprised of TOP, GND, VCC, BOTTOM ( 4 layers ).  GND layer has been assigned to the GND Net and VCC layer to VCC Net, using the creation of rectangular Shape creation, as directed in the Allegro PCB Editor Training Manual. Placing is complete and no DRC error shows up. I am ready to AutoRoute the board.

Everything goes quite well and the Board is now routed, still no DRC errors shows up.

Yet, I clearly see GND segments on the TOP and BOTTOM layers as well as VCC segments on the TOP and BOTTOM layers. It’s as if the AutoRouter did not observe the VCC Net to VCC plane assignment nor GND Net to GND plane assignment. Net Assignments to Plane where performed without error and Shape colors appeared on the screen after completion, so I have no reason to suspect the assignment went wrong.If I transfer a TOP net segment to BOTTOM where a GND segment is crossing, I get a DRC error clearly showing that both segments are in contact. Which clearly indicate that this GND segment is located on the BOTTOM layer.

What Im I doing wrong  ?  What can be the source of this problem ?

Parents

  • Hi. You need to turn GND and VCC off prior to running the autorouter. I haven't used it in some time, but there's a attribute you give nets so they don't route.

  • in reply to CadAce2K

    Thanks Lennie and CadAce2k. It's obvious to me now where the problem is. I have absolutely not given any attention to the pad structure during this continuous learning spree. Now I need to redo all parts package with revised pads. One problem that occur when I try to use the Modify Design Padstack > Single Instance or All Instances. The Pad Editor opens and I do the corrections but when I save the PAD44CIR34D file and Close the Pad Editor, Even after saving my *.brd file, close PCB Editor, re-open and then check the pads on C22 for example, well, the pads have not changed. I tried Tools > Database Check, I tried Update DRC, yet no pads are updated to the new changes made in Pad Designer. There has got to be a procedure that I am missing in order to update those pads, Any thoughts ?

  • in reply to Cailloux

    Never mind, I just found the solution. Place > Update Symbols.  

    Now I will re-autoroute and see.  thanks Again !

  • in reply to Cailloux

    Hi. The only mistake you made (and all your other steps were fine) was when in the padstack editor, before you save/exit, is to "Update the padstacks in the database" (File/Update to Design). Do that and it will save the change to your database. -Regards.

Reply Children
  • in reply to CadAce2K

    Done that too. Still didnt work ?  I would certainly appreciate you take a look at my next posted question regarding this GND connection problem. I have a feeling there is something more interfering with my autorouter.

  • in reply to Cailloux

    Hi. What's your "next posted question"?

  • in reply to Cailloux

    Hi. Aside from the padstack issue (pads to small for the drill on your inner layers), the autorouter may not be routing the GND/+12V because of property settings. Again though, simply add connect/click on the surface mount pins for GND/+12V; go away from the pad and double-click a via in. Either that, or the auto-router session is not understanding your vias.

  • in reply to CadAce2K

    I ran this little experiment. One DIP8_3, one RES400 , one capck05 packages. These packages being genuine, original from a fresh installation, not modified but verified with the Padstack editor. The board is comprised of one GND plane, one VCC plane, a very simple logic imported from Capture. The circuit is comprised of 5 Nets, which 2 of them being VCC and GND. The two planes are appropriately assigned to GND and VCC nets.

    Using the Automatic Router from Allegro PCB Editor, here are my conclusions following a lot of experimenting:

    If the [Automatic Router] is not specifically instructed to [Option > Limit via creation] , it will profusely utilize Vias to connect grounded or power nets to their respective plane layers. I am definitely missing something, for instead it would certainly be more appropriate to directly use the defined [Default Internal Pad] of a Pin within the Package instead of utilizing a Via to connect to the plane.

    It would be much appreciated if anyone with more experience can lead me to tips and tricks to better understand the situation. Cheers and thank you for any hints.

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.