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Why the Autorouter use Via to connect GND and VCC pins to Shape Plane

Cailloux

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

Parents

  • I ran this little experiment. One DIP8_3, one RES400 , one capck05 packages. These packages being genuine, original from a fresh installation, not modified but verified with the Padstack editor. The board is comprised of one GND plane, one VCC plane, a very simple logic imported from Capture. The circuit is comprised of 5 Nets, which 2 of them being VCC and GND. The two planes are appropriately assigned to GND and VCC nets.

    Using the Automatic Router from Allegro PCB Editor, here are my conclusions following a lot of experimenting:

    If the [Automatic Router] is not specifically instructed to [Option > Limit via creation] , it will profusely utilize Vias to connect grounded or power nets to their respective plane layers. I am definitely missing something, for instead it would certainly be more appropriate to directly use the defined [Default Internal Pad] of a Pin within the Package instead of utilizing a Via to connect to the plane.

    It would be much appreciated if anyone with more experience can lead me to tips and tricks to better understand the situation. Cheers and thank you for any hints.

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  • I ran this little experiment. One DIP8_3, one RES400 , one capck05 packages. These packages being genuine, original from a fresh installation, not modified but verified with the Padstack editor. The board is comprised of one GND plane, one VCC plane, a very simple logic imported from Capture. The circuit is comprised of 5 Nets, which 2 of them being VCC and GND. The two planes are appropriately assigned to GND and VCC nets.

    Using the Automatic Router from Allegro PCB Editor, here are my conclusions following a lot of experimenting:

    If the [Automatic Router] is not specifically instructed to [Option > Limit via creation] , it will profusely utilize Vias to connect grounded or power nets to their respective plane layers. I am definitely missing something, for instead it would certainly be more appropriate to directly use the defined [Default Internal Pad] of a Pin within the Package instead of utilizing a Via to connect to the plane.

    It would be much appreciated if anyone with more experience can lead me to tips and tricks to better understand the situation. Cheers and thank you for any hints.

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