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Via on SMT pin DRC

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Same net DRC off. How could we avoid that via on pin problem. Or how could we identify the DRC.


Originally posted in cdnusers.org by Vignesh

  • Under your Physical Rules, ""Set DRC modes..."" button, make sure ""Pad/Pad direct connect"" is set to ""Always"". Then under Physical Rules, ""Set values..."" button, make sure your ""Pad/pad direct connect"" is set to ""Not Allowed"". This will flag a DRC when the via is within the SMT padstack. If you have same net checking turned on, your via - pin spacing constraint will apply.

    You may want to look at SourceLink solution 11165996 for more info. I hope this helps.


    Originally posted in cdnusers.org by Padmin

  • No Its not Applicable to my query.
    I have set the, Same Net DRC ""off"". If I route with a via on a SMT pin , it should show DRC. How can I achevie this.


    Originally posted in cdnusers.org by Vignesh

  • Just to make sure... Please verify:

    1)
    Under your Physical Rules, ""Set DRC modes..."" button, you have ""Pad/Pad direct connect"" set to ""Always"" for the 'proper' constraint set?

    2)
    Under Physical Rules, ""Set values..."" button, you have ""Pad/pad direct connect"" set to ""Not Allowed"" for the 'proper' constraint set?

    If so, it would probably be best to open a Service Request with Cadence Support to look at your design.


    Originally posted in cdnusers.org by Padmin

  • Thanks I will get support from Cadence


    Originally posted in cdnusers.org by Vignesh

  • I have a similar issue. I have added my via so it is just about
    tangent to the smt pad. It actually overlaps the smt pad by a
    bit. Is there a way to have allegro not drc?


    Originally posted in cdnusers.org by Norm
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