Stats

  • Replies 5
  • Subscribers 160
  • Views 14784
  • Members are here 0
More Content

MDI routing in Gigabit Ethernet

HuLing

Hi,
I have met an problem in the routing of MDI.
It is assumed that the name of MDI nets in Gigabit Ethernet is defined as follows.
MDI0_P/MDI0_N, MDI1_P/MDI1_N, MDI2_P/MDI2_N, MDI3_P/MDI3_N.
I know signal lengths should be same within a differential signal pair. For example, MDI0_P and MDI0_N should have the same length.
I always made all pairs the same length to avoid skew due to signal delay. For example, the lengths of MDI0_P and MDI1_P are also the same.
However, I recently saw one design, in which, the signal length within the differential signal pair was the same, but the length difference between the different pairs was big. For example, the difference in length between MDI0_P and MDI1_P was about 20mm.
Was this design a mistake or was my perception a wrong?
I want to get your help on this.
Thanks.

  • excellon1

    Hi

    I believe this was an error but in certain circumstances due to board topology etc it may not be possible to maintain a complete diff pair length. From a signal perspective the physical Ethernet cable will introduce more errors in the signal path so in the big scheme of things that additional 20mm length wont amount to much.

    Certainly the goal would be on the board to maintain the integrity of the diff pairs. On these pairs the single ended impedance referenced to a plane would be 50 ohms or 100 ohms diff.

    Here is an article from TI that may help you out too.

    http://www.ti.com/lit/pdf/snla079

    All the best.

  • HuLing
    in reply to excellon1

    Hi
    Thank you for your attention.
    Yes, it is helpful. By the way, in this doc, I cannot see about length tunning between different differential pairs in Gigabit.
    So, 20mm of difference is not big problem in MDI routing of Gigabit ethernet?
    Best Regards.

  • excellon1
    in reply to HuLing

    Glad to assist HuLing.

    So the thing is the signaling. Personally I think that the extra 20MM is too much. In imperial measurement which I use that would be over 1/2 an inch.
    That extra length will introduce a very short delay. The delay will not really amount to much because the trace still has an impedance of 50 Ohms.

    I would go wit the safest route and make the diff pairs as close as possible to each other with respect to length.

    Was there a particular PHY you were using ?.

    All the best.

  • HuLing
    in reply to excellon1

    Hi,

    Thank you for your reply.

    I used KSZ9897. Please see the following url.

    https://www.microchip.com/developmenttools/ProductDetails/EVB-KSZ9897-1

    In that design, I saw the deference between the length of P4_TXRXD_P and the length of P4_TXRXA_P is 20mm.

    ( the length of P4_TXRXD_P is 73.714mm, and the length of P4_TXRXA_P  is 50.862mm)

    My question was raised by this design.

    Best Regards.

  • excellon1
    in reply to HuLing

    I see now what is going on.

    The important thing is that your basically dealing with diff pairs. The physical IC has built in terminators so the actual length of the diff pair wont pose a problem.

    When you layout the diff pairs, try using arcs as the routing method instead of the standard 45 degree type of routing, Arc based routing for High Speed design works well.

    That's a nice chip from Microchip.

    All the best.

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.