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DDR4 Trace Length Matching with Via Z-Axis Delay and Via-In-Pad

I have a design implementing two ranks of DDR4 memory consisting of 10 DRAM chips total. One rank is on the top layer and the second rank is on the bottom layer directly below. The topology is fly-by and requires many of the busses to be length matched typically to 5 or 10 mils.

Some of the data lines are routed to the top and bottom DRAM chips using via-in-pad due to routing space and convenience. The via-in-pad creates an interesting issue. The PCB thickness is 78 mils. If the trace length is to be matched to the pins connected to the via-in-pad on the top and bottom of the PCB, there would be a "trace length" difference between the top and bottom DRAM pins given that the signal layers aren't perfectly centered in the middle of the PCB. Now, I don't remember enabling "Z Axis Delay" in my OrCad PCB Designer tool, but it is enabled. I found this setting under Setup -> Constraints -> Modes -> Electrical. With this setting taking into account the via distance in the trace length, it's impossible to meet the 5 or 10 mil length matching requirement if via-in-pad is implemented.

I've done some Googling and haven't found a conclusive article or reference for including via z-direction in the DDR4 routing trace length matching. I *think* this function was enabled by default. Is via z-direction distance typically included when trace matching for topologies like DDR4/fly-by? Via-in-pad seems to be pretty common for DDR4 routing from what I can tell. It's curious I haven't been able to find more info on the subject.

My toolset is OrCAD PCB Designer Professional 17.4-2019 S016.

excellon1 over 4 years ago

Hi,

Here is the link to a good document.

https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn4040_ddr4_point_to_point_design_guide.pdf

Page 19 talks about the vias and timing budget which may help you out. They indicate that the via Z length should be considered.

Generally for Ram Micron would be a good place for info as they have some great technical docs.

There was also a good video that talks about using the feature in Orcad which came out in 17.2 hotfix-48. that might help too

https://www.youtube.com/watch?v=91D8sktUXD4

All the best.
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redwire over 4 years ago

Usually z-axis rule is off and is license-based. Sounds like it was on from a previous design... Not sure why you think VIP is any different on z-axis delay than a regular via...? Also, if you're being told to consider "5 mils" on DDR4? Wow.... you need to look into fiber-weave effect based skew...it'll be there.
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Gipper over 4 years ago in reply to excellon1

Thanks for sharing. I found that document as well.

My takeaway from the via paragraph on page 19 was to ensure the via count for each matched trace be the same. This makes sense to me. I have not yet found anything specific for z-length mismatches using via-in-pad. Via-in-pad is used fairly commonly for DDR, so I suspect this concern may not be as severe as I originally thought.
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avant over 4 years ago

One thing that may help is that the data pins can be swapped within one bank. This will allow the ddr pins on the top side directly over the ddr pins on the bottom side.
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Gipper over 4 years ago in reply to avant

Yes, I am using "bit-swizzling" on some of the data pins that allow it. This also allows me to have a direct via-in-pad connection to some pins that are directly over each other top/bottom.
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