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  3. Why does my layer name change in XSection when importing...

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Why does my layer name change in XSection when importing a netlist from OrCAD to PCB Designer

thomasli
thomasli over 4 years ago

Hi

I just stumbled across a strange behaviour. I have a design where I know that the names of the layers had an error (typo) a long time ago (say, July 2020). We fixed that in august 2020 in the PCB Designer. Now we're redesigning the board, have made some changes in the schematic and created a new netlist. When I now import the netlist, the layer name will revert to the faulty one from July 2020.

Why is that and how can I ensure that this doesn't happen? I don't quite see why a layer name should be transferred from schematic to PCB.

My current version is 17.4-2019 S016.

Regards,

Thomas

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  • AvengerThanos
    AvengerThanos over 4 years ago

    What approach are you following to import the netlist? is it Import - Logic/Netlist from PCB editor or PCB - Update layout from schematics. If you are using the PCB editor approach then try the PCB - Update layout from schematics and make sure the board pointed is the Aug2020 version before netlisting.

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  • thomasli
    thomasli over 4 years ago in reply to AvengerThanos

    Hi AvengerThanos

    It took me a while to figure out what was happening. I'm using the Create Netlist from OrCAD and then import it via File -> Import -> Netlist in PCB Designer. 

    Apparently (and this is something I was not aware of) it takes the layer names from the Constraints dialog in the schematic. It appears that the layer names were corrected in the PCB later on and when I re-spun the board and created a new netlist, the net names were overwritten (it would do this each time I would create a netlist). Once I corrected the name in the Constraints Dialog of the schematic, it would use the corrected name. So apparently the name is somehow transferred in the netlist (I wasn't able to find it in the netlist text files though). 

    I think I'll somehow need to tell OrCAD NOT to take the constraints from the schematic and just use those from the Layout because the schematic constraints were just an initial "best guess" and the real constraints have been defined in the layout. I have a different project where I never used the schematic constraint manager and there are no such issues. I'm trying to follow a purely schematic -> PCB approach (no transfer from PCB to schematic).

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