Stats

  • Replies 2
  • Subscribers 160
  • Views 10726
  • Members are here 0
More Content

Same net spacing DRC error handling

ichliebedich

Hi all

I set the 0.2mm of SMD pin to BB via at the samce Net spacing rule

and I tested like below. each couple of left one is SMD pin and right one is BBvia

I set the 0.2mm spacing. so left column set occurring DRC error is correct.

but when the SMD pin is coverd by BBvia over half, DRC error was not occur as you can see the right column set

but if BBvia take apart from center of the SMD pin, the DRC error occurred again, before then DRC error was not happened..

How can I handle the that DRC error marker without waive DRC?

I don't want to occur DRC marker when SMD pin and BBvia are contacted even slightly

but if they are apart, same net spacing Rule must be effected.

(pin and via are located same layer)

reagard

  • steve

    This is a via in pad rule which is enabled differently. Take a look at Via in Pad Rules (parallel-systems.co.uk)

  • ichliebedich
    in reply to steve

    thank you! I checked that document but this case is not work..  because this design should set the "same Net Spacing" rule as well.. if center of via take off from smd pin boundary, the same net spacing rule was applied automatically.  doesn't any way to ignore the DRC when pin and via are touched each other?

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.