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  3. Vias and footprint

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Vias and footprint

LOR75
LOR75 over 3 years ago

Hello,

I have to design a QFN64 footprint with a thermal pad at the center of the component; obviously this pad must be connected to the ground plane of the bottom layer by using vias.

What's the best way to put vias?

1 - Put vias in the pad during "pad  designer session" so when i place the pin in the foorprint the vias are already inserted in the footprint;

2 - Place a filled square area for the central pad (without vias) and then place vias  during the routing of the board over the filled square

what do you usally do? Are these solution identical for the final result?

Best regards.

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  • excellon1
    excellon1 over 3 years ago in reply to Wild

    Hi thomasli.

    Here is an example, "RF Semiconductors" Go ahead and have your designer put down vias where they want. More than likely the customer wont be happy.

    Follow the "Data Sheet" they are created for a very good reason ! as Wild indicated.

    https://www.nxp.com/docs/en/data-sheet/MMZ25333B.pdf

    Page 14

    As was indicated one of the best methods is to use the pad designer to create the holes in the bonding pad which represent vias. On such things you never ever what a designer
    bit twiddling vias because they feel like they know better. Putting the holes directly into the pad that is used to create the footprint will remove this barrier and keep design integrity.

    Honestly there is no way in hell I would want any designer creating such footprints that did not follow the data sheet in particular for critical applications. The negative down side
    has a big potential, so a word from the wise, Follow the data sheet. If you have any doubts, contact the part manufacturer for additional detail, it is not wise to assume you know
    better !.

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  • thomasli
    thomasli over 3 years ago in reply to excellon1

    Hi excellon

    That's a very good example for what I am trying to say: Yes, there is some sort of a via structure on pg. 14 and each designer would put a number of vias to the exposed pad - probably even in some kind of arrangement like that - but nowhere in that datasheet there is any dimensioning for that structure - neither is in the actual package drawing. Do I really have to create the exact structure by measuring from the PDF even if the manufacturer obviously doesn't care enough to dimension it?

    Again, I'm not saying do not care at all. There are many ICs where I certainly would never route a trace below (PD comes to mind). But, there are many ICs where the via layout is probably not that critical although it's specified in the datasheet. If it is, tell me, give me measures, state it explicitly, show me where the bond wires end. In that case, there is no room for doing anything differently. On the other hand, I've come across EVKs from the manufacturer which violate the layout (!) guidelines the manufacturer himself has specified in the datasheet (and not just by a little).

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  • Wild
    Wild over 3 years ago in reply to thomasli

    Have you tried registering on the device manufacturer website and looked for the datasheet and supporting documents for the part in question?  For the product lines that I have supported we have detailed user guides that provide engineering details including engineering details such as SI rules, capacitance rules and thermal rules for the carrier class products.  We have provided application boards platforms with full documentation.

    May I suggest you try reaching out to your device supplier and asking if such details exist?  Here's an example. last year I was designing a device high frequency characterization platform.  The first rev had an issue with the balun we using so we could make single ended to differential measurements.  We were having issues with frequency roll up and insertion loss.  I reached out to Minicurcuits (bauln manufacture) and I spoke with an FAE would spent time looking at the schematic and the PCB design and found issues that we corrected.  

    I understand that this assumes you are not a contract house, but the engineer responsible should do their do diligence and obtain details of the device used, at least this was how we were trained in the Ma Bell days. Slight smile

    Another note:  join the SMTA, they have so many great white papers on topics such as Paste Mask studies and thermal studies.  Alot of the papers and articles I have seen come from this resource.

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  • excellon1
    excellon1 over 3 years ago in reply to thomasli

    Hi

    On page 5 of the data sheet they show a reference PCB for the application circuit so this reference circuit is where the PCB Footprint was derived from. On a data sheet typically there is the electrical spec of the part and in most cases a land pattern. I agree that it would be nice for the land pattern to call out the via holes size but depending on the use case of the device the via holes may not be needed. In that particular part from NXP the via holes serve 2 functions, Gnd & heat removal so as to keep the thermals in check.

    Usually in anything that is going to drop current and generate heat you will usually see a similar land pattern with the via holes.

    As with all things some work is required, the best you can do is follow the datasheet. You would also need perhaps an engineering background to fully understand the concept too. Less obvious are things like the PCB Thickness & plating not to mention the foil thickness of the copper. You wont find PCB foil thickness on a data sheet. Point here is the reference circuit is in essence supplemental information to realize a reliable PCB for the intended part. Golden rule is. If a reference circuit is available from a manufacturer, ask for the drawing !

    All the best.

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