Vias and footprint

I have done hundreds of BTC component designs for a large company, we always use the pad designer to embed the vias in the ePad.  BTW, the biggest issue with BTC design is the PM (Paste Mask), if you don't have a copy of the IPC7093 Standard (2020) you should.  It covers the PM design quit well. 

We only place the pad into the footprint and leave it up to the designer to place the vias in the design. I cannot think of a reason why the vias should be exactly where they are in the datasheet (typically it's transferring heat or large current). If you place them into the pad, you may obstruct routing later on.

We (IC manufacturer) spend a lot of effort in thermal simulation using tools such as Ansys Icepak and Siemans Flotherm to develop the footprints and thermal models.  The recommendations in our data sheets are fully vetted through the simulations and validation.  So to blindly say not to follow the manufacturers guidelines within their data sheet is not a good engineering practice.  We can only hope that the engineers that are routing signals under the BTC and moving/removing thermal vias does the do diligence of a board level simulation before going to manufacture.

We have had so many field returns that have turned out to be PCB design and assembly related issues, included over pasting, poor routing issues... etc..  I would advise against the above posters information unless you have the tools to do the signal analysis, thermal and circuit simulations.  

As we used to say in Bell Labs, Mange by Fact.

Hi Wild, 

it's great to hear from someone coming from the "other" side as we're not IC designers (in no way at all). Please understand that I didn't say "do not follow the guidelines", I just said that there might be room for optimizations when doing the board layout. Take the following part for example: https://www.ti.com/product/MSP430FR2676. I just selected it because it's in a standard QFN package .. there are about a few hundred other parts - completely different functions - which use the very same package drawing (same TI drawing ID). I have a hard time believing that the vias must be placed at exactly the locations specified.

Since you also mention "over pasting". I have yet to find a part which specifies the exact volume of paste. Of course, usually a paste mask drawing is specified, but how thick does the stencil have to be? And that's just one thing that is crucial for the amount of paste which is applied. Also, the type of paste can make some difference.

I am pretty sure that there are certain ICs to which the exact placement is crucial but I do also think that that's a minority. In most cases I've come across the exposed pad vias are simply for heat transfer into the board, one time I've even come across an IC where the package actually had an exposed pad at the bottom but the datasheet explicitly mentioned that is mustn't be connected to anything - not even an isolated, electrical pad.

If you don't mind: can you give an example of an IC you (or your colleagues) designed where the via placement is crucial? I'd really (!) be interested in the background a bit if you have the time to elaborate on that - it's never too late to learn something new.

Sorry for the slow response work got in the way.

Unfortunately I have found that all the documents that we have written have been removed from the web and are under NDA .  We release these documents to our customers with valid NDA's and we are incorporating the stencil guidelines into our product documents in my organization.

I was able to find a few on the web such as: https://www.slideshare.net/GregCaswell2/understanding-thecriticalityofstencilaperturedesignandimplementationforaqfnpackage This document  has been updated internally.

Please look at IPC7093 (2020) and you will see the guidelines that we reference for ePad design.

My guidelines that we use are based on DOE experiments and IPC7901 and IPC7902 testing.  I wish I could share these, but are Proprietary.  All our results for BTC mounting align with the IPC7093 (2020).

Note: The are documents from other companies that deal with the typical paste design to prevent over pasting that you can find on the web, i.e. NXP document AN1902 rev.9 April 2021 

https://www.google.com/url?sa=i&url=https%3A%2F%2Fc44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com%2F2018%2F08%2FAN3015B-Amkor-DRMLF-App-Note-0818.pdf&psig=AOvVaw0mrB4VTOv_ElWmeQ1d0jBF&ust=1632497570362000&source=images&cd=vfe&ved=0CAcQjhxqFwoTCIiZrcK1lfMCFQAAAAAdAAAAABAP

Also note the target stand off height is achieved using a 5 mil stencil, this should product a bond line thickness of about 63um.  This target is mid range of the specification in the IPC7093 standard to achieve a reliable package attachment.

Here's a design of a IO Pin on a typical package from our guidelines (Datasheet), so now you have seen a Stencil that defines the area and volume of paste for a non wettable flank BTC IO pin.

There are so many more details on why we design ePad via;s and PM such as out gassing, I just don't have the time to add them.

Summary, get a copy of the IPC7093 standard (2020) it really is a great document.