Vias and footprint

We only place the pad into the footprint and leave it up to the designer to place the vias in the design. I cannot think of a reason why the vias should be exactly where they are in the datasheet (typically it's transferring heat or large current). If you place them into the pad, you may obstruct routing later on.

We (IC manufacturer) spend a lot of effort in thermal simulation using tools such as Ansys Icepak and Siemans Flotherm to develop the footprints and thermal models.  The recommendations in our data sheets are fully vetted through the simulations and validation.  So to blindly say not to follow the manufacturers guidelines within their data sheet is not a good engineering practice.  We can only hope that the engineers that are routing signals under the BTC and moving/removing thermal vias does the do diligence of a board level simulation before going to manufacture.

We have had so many field returns that have turned out to be PCB design and assembly related issues, included over pasting, poor routing issues... etc..  I would advise against the above posters information unless you have the tools to do the signal analysis, thermal and circuit simulations.  

As we used to say in Bell Labs, Mange by Fact.

Hi Wild, 

it's great to hear from someone coming from the "other" side as we're not IC designers (in no way at all). Please understand that I didn't say "do not follow the guidelines", I just said that there might be room for optimizations when doing the board layout. Take the following part for example: https://www.ti.com/product/MSP430FR2676. I just selected it because it's in a standard QFN package .. there are about a few hundred other parts - completely different functions - which use the very same package drawing (same TI drawing ID). I have a hard time believing that the vias must be placed at exactly the locations specified.

Since you also mention "over pasting". I have yet to find a part which specifies the exact volume of paste. Of course, usually a paste mask drawing is specified, but how thick does the stencil have to be? And that's just one thing that is crucial for the amount of paste which is applied. Also, the type of paste can make some difference.

I am pretty sure that there are certain ICs to which the exact placement is crucial but I do also think that that's a minority. In most cases I've come across the exposed pad vias are simply for heat transfer into the board, one time I've even come across an IC where the package actually had an exposed pad at the bottom but the datasheet explicitly mentioned that is mustn't be connected to anything - not even an isolated, electrical pad.

If you don't mind: can you give an example of an IC you (or your colleagues) designed where the via placement is crucial? I'd really (!) be interested in the background a bit if you have the time to elaborate on that - it's never too late to learn something new.

Hi Wild, 

it's great to hear from someone coming from the "other" side as we're not IC designers (in no way at all). Please understand that I didn't say "do not follow the guidelines", I just said that there might be room for optimizations when doing the board layout. Take the following part for example: https://www.ti.com/product/MSP430FR2676. I just selected it because it's in a standard QFN package .. there are about a few hundred other parts - completely different functions - which use the very same package drawing (same TI drawing ID). I have a hard time believing that the vias must be placed at exactly the locations specified.

Since you also mention "over pasting". I have yet to find a part which specifies the exact volume of paste. Of course, usually a paste mask drawing is specified, but how thick does the stencil have to be? And that's just one thing that is crucial for the amount of paste which is applied. Also, the type of paste can make some difference.

I am pretty sure that there are certain ICs to which the exact placement is crucial but I do also think that that's a minority. In most cases I've come across the exposed pad vias are simply for heat transfer into the board, one time I've even come across an IC where the package actually had an exposed pad at the bottom but the datasheet explicitly mentioned that is mustn't be connected to anything - not even an isolated, electrical pad.

If you don't mind: can you give an example of an IC you (or your colleagues) designed where the via placement is crucial? I'd really (!) be interested in the background a bit if you have the time to elaborate on that - it's never too late to learn something new.

Sorry for the slow response work got in the way.

Unfortunately I have found that all the documents that we have written have been removed from the web and are under NDA .  We release these documents to our customers with valid NDA's and we are incorporating the stencil guidelines into our product documents in my organization.

I was able to find a few on the web such as: https://www.slideshare.net/GregCaswell2/understanding-thecriticalityofstencilaperturedesignandimplementationforaqfnpackage This document  has been updated internally.

Please look at IPC7093 (2020) and you will see the guidelines that we reference for ePad design.

My guidelines that we use are based on DOE experiments and IPC7901 and IPC7902 testing.  I wish I could share these, but are Proprietary.  All our results for BTC mounting align with the IPC7093 (2020).

Note: The are documents from other companies that deal with the typical paste design to prevent over pasting that you can find on the web, i.e. NXP document AN1902 rev.9 April 2021 

https://www.google.com/url?sa=i&url=https%3A%2F%2Fc44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com%2F2018%2F08%2FAN3015B-Amkor-DRMLF-App-Note-0818.pdf&psig=AOvVaw0mrB4VTOv_ElWmeQ1d0jBF&ust=1632497570362000&source=images&cd=vfe&ved=0CAcQjhxqFwoTCIiZrcK1lfMCFQAAAAAdAAAAABAP

Also note the target stand off height is achieved using a 5 mil stencil, this should product a bond line thickness of about 63um.  This target is mid range of the specification in the IPC7093 standard to achieve a reliable package attachment.

Here's a design of a IO Pin on a typical package from our guidelines (Datasheet), so now you have seen a Stencil that defines the area and volume of paste for a non wettable flank BTC IO pin.

There are so many more details on why we design ePad via;s and PM such as out gassing, I just don't have the time to add them.

Summary, get a copy of the IPC7093 standard (2020) it really is a great document.

Hi thomasli.

Here is an example, "RF Semiconductors" Go ahead and have your designer put down vias where they want. More than likely the customer wont be happy.

Follow the "Data Sheet" they are created for a very good reason ! as Wild indicated.

https://www.nxp.com/docs/en/data-sheet/MMZ25333B.pdf

Page 14

As was indicated one of the best methods is to use the pad designer to create the holes in the bonding pad which represent vias. On such things you never ever what a designer
bit twiddling vias because they feel like they know better. Putting the holes directly into the pad that is used to create the footprint will remove this barrier and keep design integrity.

Honestly there is no way in hell I would want any designer creating such footprints that did not follow the data sheet in particular for critical applications. The negative down side
has a big potential, so a word from the wise, Follow the data sheet. If you have any doubts, contact the part manufacturer for additional detail, it is not wise to assume you know
better !.

Hi excellon

That's a very good example for what I am trying to say: Yes, there is some sort of a via structure on pg. 14 and each designer would put a number of vias to the exposed pad - probably even in some kind of arrangement like that - but nowhere in that datasheet there is any dimensioning for that structure - neither is in the actual package drawing. Do I really have to create the exact structure by measuring from the PDF even if the manufacturer obviously doesn't care enough to dimension it?

Again, I'm not saying do not care at all. There are many ICs where I certainly would never route a trace below (PD comes to mind). But, there are many ICs where the via layout is probably not that critical although it's specified in the datasheet. If it is, tell me, give me measures, state it explicitly, show me where the bond wires end. In that case, there is no room for doing anything differently. On the other hand, I've come across EVKs from the manufacturer which violate the layout (!) guidelines the manufacturer himself has specified in the datasheet (and not just by a little).

Have you tried registering on the device manufacturer website and looked for the datasheet and supporting documents for the part in question?  For the product lines that I have supported we have detailed user guides that provide engineering details including engineering details such as SI rules, capacitance rules and thermal rules for the carrier class products.  We have provided application boards platforms with full documentation.

May I suggest you try reaching out to your device supplier and asking if such details exist?  Here's an example. last year I was designing a device high frequency characterization platform.  The first rev had an issue with the balun we using so we could make single ended to differential measurements.  We were having issues with frequency roll up and insertion loss.  I reached out to Minicurcuits (bauln manufacture) and I spoke with an FAE would spent time looking at the schematic and the PCB design and found issues that we corrected.  

I understand that this assumes you are not a contract house, but the engineer responsible should do their do diligence and obtain details of the device used, at least this was how we were trained in the Ma Bell days. 

Another note:  join the SMTA, they have so many great white papers on topics such as Paste Mask studies and thermal studies.  Alot of the papers and articles I have seen come from this resource.

Hi

On page 5 of the data sheet they show a reference PCB for the application circuit so this reference circuit is where the PCB Footprint was derived from. On a data sheet typically there is the electrical spec of the part and in most cases a land pattern. I agree that it would be nice for the land pattern to call out the via holes size but depending on the use case of the device the via holes may not be needed. In that particular part from NXP the via holes serve 2 functions, Gnd & heat removal so as to keep the thermals in check.

Usually in anything that is going to drop current and generate heat you will usually see a similar land pattern with the via holes.

As with all things some work is required, the best you can do is follow the datasheet. You would also need perhaps an engineering background to fully understand the concept too. Less obvious are things like the PCB Thickness & plating not to mention the foil thickness of the copper. You wont find PCB foil thickness on a data sheet. Point here is the reference circuit is in essence supplemental information to realize a reliable PCB for the intended part. Golden rule is. If a reference circuit is available from a manufacturer, ask for the drawing !

All the best.