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Overlapping a slot and a hole in a footprint (and copper shapes + stitching vias too!)

bengelJF

I'm a few weeks in on learning the PCB side of OrCAD. As practice, I'm creating a footprint for a VPX backplane guide pin:

The footprint calls for either a hole or slot that overlaps with the main hole as a method to key the pin. I've elected for a slot as seen above. Unsurprisingly, I'm getting a pin-to-pin DRC error - how would I clear this error? (It's a weird edge case, so I accept that the answer may be to just ignore it and waive the error.)

The other DRC errors are thru pin-to-shape errors. I have a copper shape (the "C") on the top and bottom layers to ground out the pin, and am stitching the shapes together with vias. The error goes away for the one pin I have set up to provide connectivity when the footprint is brought into a board file. However, the errors persist for the eight remaining pins, which are mechanical pins to avoid having 9 total pins on each schematic symbol. One way to solve this would be to make them numbered electrical pins as well, and add them as invisible power pins on the schematic symbol - is there a more elegant way to do this without changing the schematic symbol?

  • +1

    Hi,

    You don't have to define a slot as a physical pin or padstack in the editor. There is another way. Just draw a line of a suitable width on the Class "Board Geometry" SubClass " NCroute_Path", when you generate your drill file and routes the PCB editor will create a route path for the Line that is representing the slot.

    That should take care of the overlapping pins since there is no pin for the slot.

    There is not a good way to handle the stitching vias really. Ideally you would want these to have a net so that means a pin. One could create them as mechanical but I think having an associated net such as ground is better and then drive that from the schematic. Only option there is have hidden pins on the schematic, though one could make a fairly ok symbol to represent them.

    Maybe that will help you out.

  • +1 in reply to excellon1

    Try using vias instead of mechanical pins (Layout - Connections then double click) the via is setup as you would normally through Constraint Manager - Physical. Once this is used in a board the vias will take on the same net as the pin and you won't see any DRC's,

  • 0 in reply to steve

    Thanks to the both of you! Replacing the slot-as-padstack with slot-on-NCRoute removed that DRC, and replacing the stitching vias with actual vias instead of mechanical pins removed those DRCs as well. The only DRC I have left is the thru pin to shape spacing with the actual named pin that provides connectivity. The error goes away when the symbol is used in the board design as the shape inherits the net from the thru pin. (I think?)

    Might as well hijack my own thread - now the stitching vias throw a soldermask to via spacing DRC, where the constraint and actual values are both 0. The vias are entirely within the soldermask opening from the "base" padstack that makes up the pin. However, applying what we learned above about mechanical pins vs. vias to an older footprint I did with a similar setup doesn't throw errors. It looks like to prevent this error from occurring, I have to separate the solder mask opening from the padstack and change it to a shape drawn on the package geometry layer, is that correct?

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