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How to export ascii file (.asc) from Allegro PCB ? (ODB++ ?)

ichliebedich

Hi All

I have to export ascii format (.asc) like below from my design designed by Allegro PCB to the Fab

so I searched it the way to export asc file, there were some data using by ODB++

so I installed ODB++ software and tried to export ODB++ data

but I don't know about ODB++ and I don't know how to use it

but I couldn't find the .asc file at the output files.

How can I export  .asc file?

regard

  • 0

    You can't export a .asc file containing all the design data, I think those are the ascii files output from Seimens EDA/Mentor Graphics PADS tool

    The output from the ODB++ Inside tool is an ODB++ job structure, which is a directory structure of ascii files 

  • 0 in reply to ichliebedich

    An ODB++ design output is a directory structure of ascii files that can be read by CAM tools, such as Valor NPI, Wise Gerbtool, etc...

    Below is the directory structure for the Cadence example design cds_routed.brd:

    D:\Cadence\SPB_17.4\share\pcb\examples\board_design>tree cds_routed
    Folder PATH listing for volume New Volume
    Volume serial number is 902D-8197
    D:\CADENCE\SPB_17.4\SHARE\PCB\EXAMPLES\BOARD_DESIGN\CDS_ROUTED
    ├───fonts
    ├───input
    ├───matrix
    ├───misc
    ├───output
    ├───steps
    │ └───stp
    │ ├───eda
    │ ├───layers
    │ │ ├───bottom
    │ │ ├───comp_+_bot
    │ │ ├───comp_+_top
    │ │ ├───dielectric_0
    │ │ ├───dielectric_1
    │ │ ├───dielectric_2
    │ │ ├───drill
    │ │ ├───gnd
    │ │ ├───outline
    │ │ ├───top
    │ │ └───vcc
    │ └───netlists
    │ └───cadnet
    ├───symbols
    ├───user
    ├───wheels
    └───whltemps

    below is the contents of the top etch layer:

    D:\Cadence\SPB_17.4\share\pcb\examples\board_design>dir cds_routed\steps\stp\layers\top
    Volume in drive D is New Volume
    Volume Serial Number is 902D-8197

    Directory of D:\Cadence\SPB_17.4\share\pcb\examples\board_design\cds_routed\steps\stp\layers\top

    03/11/2022 12:08 PM <DIR> .
    03/11/2022 12:08 PM <DIR> ..
    03/11/2022 12:08 PM 118 .attrlist.sum
    03/11/2022 12:08 PM 121 .features.sum
    03/11/2022 12:08 PM 1,519 attrlist
    03/11/2022 12:08 PM 105,532 features
    4 File(s) 107,290 bytes
    2 Dir(s) 44,131,692,544 bytes free

    Below is the end of 2 of the files containing design data:

    D:\Cadence\SPB_17.4\share\pcb\examples\board_design>tail cds_routed\steps\stp\layers\top\attrlist
    .etm_step_x = 0
    .etm_step_y = 0
    .etm_thickness = 20
    .inp_x_scale = 1
    .inp_y_scale = 1
    .se_coupon_max_size = 0
    .se_coupon_min_size = 0
    .se_coupon_slot_angle = 0
    .se_coupon_slot_length = 0
    .se_coupon_dist = 0

    D:\Cadence\SPB_17.4\share\pcb\examples\board_design>tail cds_routed\steps\stp\layers\top\features
    P 2.2165 1.568 3 P 0 8 0;1=1,2=1;ID=5175
    P 1.912 1.8385 3 P 0 8 0;1=1,2=1;ID=5177
    P 1.697 2.3 11 P 0 8 0;0,1=0,2=0;ID=5183
    P 1.8 2.197 11 P 0 8 270.312;0,1=0,2=0;ID=5184
    P 2.103 2.25 11 P 0 8 0.312;0,1=0,2=0;ID=5185
    L 2.7565 0.86 2.7575 0.859 0 P 0;;ID=5186
    P 0 0 5 P 0 8 0;1=11,2=0;ID=5187
    P 0 3.7 5 P 0 8 0;1=11,2=0;ID=5189
    P 3.1 3.7 5 P 0 8 0;1=11,2=0;ID=5191
    P 3.1 0 5 P 0 8 0;1=11,2=0;ID=5193

    D:\Cadence\SPB_17.4\share\pcb\examples\board_design>

  • 0 in reply to DavidJHutchins

    What is the acceptable way to transmit the ODB++ files? Zip the directory?

  • 0 in reply to smiller

    Most fab houses are used to getting the .tgz files output from 'odb_out', configured with the 'Create Archive' option

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