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Line to Thru Pin Spacing DRC error when I route a THP on the bottom layer

I have a custom made through hole footprint for which I got a DRC error when I route from that pin: NET SPACING CONSTRAINTS Constraint Type. The actual value is 0mm, which means that the track is connected to the pin as intended, just somehow the DRC thinks it is an error. The via is plated, it shows the same net in the PCB editor as the top side. Which option or constraint shall I look at to debug it? Could it be an issue in the padstack?

I am new to Allegro and this would be my first design.

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