Stats

  • State Not Answered
  • Replies 2
  • Subscribers 160
  • Views 4923
  • Members are here 0
More Content

Same Net Spacing - Thru Via To SMD Pin

Fredda

I'll be using plugged vias and thus I want to allow placing vias in pads and close to a pad if they are connected with a copper trace. How do I set up the constraints in the best way for this?

Problem I'm having is that if I turn off "Same Net Spacing  - Thru Via To SMD Pin", both of the below are allowed, but I want the first one to give me a DRC error. Via, pad and shape are all on the same net here.

/F

  • steve
    0

    YOu can look at the Physcial rules for Pad-Pad Connect but also check this out:- Via in Pad Rules (parallel-systems.co.uk)

  • Fredda
    0 in reply to steve

    Thanks. I've been experimenting with the Via at SMD pin constraints and they will give an error in the following situation:

    The "Same Net Spacing  - Thru Via To SMD Pin" will also give an error here although the Pad-Pad Connect is set to ALL_ALLOWED. Probably because the via connect point doesn't lie within the extents of the pad. So question is why the cline doesn't form a proper connection that gets rid of the error?

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.