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  3. Reannotating Schematic caused errors

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Reannotating Schematic caused errors

Neil mustafa
Neil mustafa over 3 years ago

Hello All,

I had an issue with my reference designators on my schematic, in order to make them consistent, I decided to reset part references and then reannotate all the parts in incremental order, so far so good.

Now since I already had a board made with the netlist generated from the previous version of this schematic, I tried to recreate a netlist and using that board I had as an input board. Now, this generated errors and I am not sure how to solve it.

Here is what I get in the session log:

------ Oversights/Warnings/Errors ------


#1 ERROR(SPMHNI-191): Device/Symbol check error detected.

ERROR(SPMHNI-195): Symbol 'SOT89' for device 'MOSFET_N_GDSD_SOT89_TN2510N8-G' is missing pin '4'.

------ Library Paths ------
MODULEPATH = .
C:/Cadence/company/pcb/modules

PSMPATH = .
symbols
padstacks
C:\Cadence\company\pcb\padstacks
C:\Cadence\company\pcb\padstacks\student
C:\Cadence\company\pcb\padstacks\smartstart
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU_HOLE
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU_HOLE

PADPATH = .
symbols
padstacks
C:\Cadence\company\pcb\padstacks
C:\Cadence\company\pcb\padstacks\student
C:\Cadence\company\pcb\padstacks\smartstart
J:/CADENCE/LIBS/PCB/PADS/
C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols/
C:/Users/nmustafa/Custom_Symbols/
J:/CADENCE/LIBS/
J:/CADENCE/LIBS/SCH/LAP TEMPLATES/
J:/CADENCE/LIBS/PCB/SYMBOLS/SMT
J:/CADENCE/LIBS/PCB/SYMBOLS/THRU
_HOLE


------ Summary Statistics ------


#2 Run stopped because errors were detected

netrev run on Jul 26 12:02:05 2022
DESIGN NAME : 'XXX_SCH'
PACKAGING ON Mar 2 2016 00:37:24

COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON

2 errors detected
No oversight detected
No warning detected

cpu time 0:22:54
elapsed time 0:00:13

INFO(ORCAP-32005): *** Done ***
INFO(ORCAP-2383): Autobackup started at 2022-07-26.12:02:19. The autobackup file name is C:\USERS\NMUSTAFA\DOCUMENTS\NEW 2 LEVEL LIGHT\28VWDIM_EMERGENCY\NEW\XXX_SCH_1.DBK.
INFO(ORCAP-2384): Autobackup finished at 2022-07-26.12:02:19. The autobackup file name is C:\USERS\NMUSTAFA\DOCUMENTS\NEW 2 LEVEL LIGHT\28VWDIM_EMERGENCY\NEW\XXX_SCH_1.DBK.

Now, I haven't changed the part and it was working fine before, all I did was reset the annotation and automatically annotate in ascending order. Opening, the symbol where it says pin 4 is missing, it is actually still there!

I looked at whether the pin numbers have changed on the updated schematic, nope, they are all still in the same order.

Any ideas or thoughts would be highly appreciated.

Schematic BEFORE:

Schematic after:

The error is complaining about the part Q7 in the first pic or Q5 in the second picture.

Here is the footprint SOT89 which says pin 4 is missing , but as shown in the picture below it is still there. There were no issues with it as well before I reannotated my schematic

Please help me out.

Best regards.

Neil Mustafa.

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