• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X PCB Editor
  3. Removing VG DRC

Stats

  • State Verified Answer
  • Replies 5
  • Subscribers 159
  • Views 7306
  • Members are here 0
More Content

Removing VG DRC

JITHINDEV
JITHINDEV over 2 years ago

Hi all,

Is there any fabrication difficulties or reliability issues when ignoring the VG DRC?
image attached for reference


Regards,
Jithindev

  • Sign in to reply
  • Cancel
  • TCHA
    0 TCHA over 2 years ago

    Generally you should not get a fabrication or reliability issue if the vias or the via and pin are well spread out. Incase the vias or via and the pin comes too close to each other or overlaps then you could see issues in fabrication. 

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • JITHINDEV
    0 JITHINDEV over 2 years ago in reply to TCHA

    Hi TCHA,

    Thankyou for the reply. so you meant we can ignore the Via Gap DRC. 

    Regards,
    Jithindev

    • Cancel
    • Vote Up +2 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • TCHA
    0 TCHA over 2 years ago in reply to JITHINDEV

    The BB Via gap is mainly done for manufacturing reasons. It could be the BB vias are first created on individual layers before creating the layer stackup, so to have a minimum gap between any two vias in a stack-up, this gap has been introduced.


    You can however choose to add the 'BBVIA_SEPARATION' property to specify the span of layers where the MIN VIA GAP check is applied. By default, the span is infinite, which means that all the non-connected vias are checked even if these appear on the opposite sides of the design. So with a proper value set for BBvia_separation, you can choose to avoid the BB Via Gap DRC errors

    The BBVIA_SEPARATION is a design-level integer property. You can also set the value from through Setup > Constraint > Modes > Design/General.

    • Cancel
    • Vote Up +2 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • JITHINDEV
    0 JITHINDEV over 2 years ago in reply to TCHA

    Hi TCHA,

    Better if you briefly explain the manufacturing reason. since I have failed to find any.

    Thank you
    Jithindev

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • TCHA
    +1 TCHA over 2 years ago in reply to JITHINDEV

    The Blind/Buried drill depths can sometimes vary causing the drill to pass beyond the drill stop layer into the adjacent dielectric layer. In such cases, a drill can get close to an adjacent layer drill start or stop layer causing a short during lamination cycles. Issues are not limited to fabrication only. It also can occur during assembly with the PCB going through multiple heat cycles. With todays modern fabrication processes these may not be a big concern but the rule is still relevant. Before sending out the board, you should consult your fabrication vendor.

    As discussed earlier about the BBVIA_SEPARATION property, note, it is not realistic to set a Min Via Gap without also setting the BBVIA_SEPARATION. This is because a via drilled from Layer 1 to 2 will not be anywhere near a via drilled from Layer 12 to 11 so seeing a DRC in those cases will not be required.

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Reject Answer
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information