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  3. How to prohibit drilling a hole in a hole (via GND inside...

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How to prohibit drilling a hole in a hole (via GND inside via GND) (see images)?

daivermaster
daivermaster over 2 years ago

Allegro PCB Editor 2022
Place > Via array

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  • Schulz Jordan
    0 Schulz Jordan over 2 years ago

    Enable DRC check & increase the via to via offset

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  • John T
    0 John T over 2 years ago

    By tool default, "Same Net DRC" will not produce DRCs for pins or vias that are 100% directly connected (overlap connection not requiring a cline). These type connections are considered to have been intentionally done by you for reasons such as thermal vias etc. To change this default behaviour go to Setup > Constraints > Physical. and set the Pad-Pad Connect to NOT_ALLOWED. 

    SPB 17.4 Hotfix 28 (QIR4) onward one can also create the DFF Constraint sets for hole-to-hole or pad-to-pad using Manufacturing > Design for Fabrication > DFF constraint set > Copper spacing 

    Be sure to enable these same-net checks in analysis modes under DFF > Copper Spacing. 

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