Package to Package Spacing Errors How to Fix

Hello all,

I am facing an issue that I haven't figured out yet how to solve and would love to get some tips on that. So, after routing my Board , I had 0 errors. But due to thermal considerations , I poured copper on all 4 layers on my board and assigned them all to a dummy net in order to help with thermal management. What I did then , was copy a Plated through hole / Via and placed it all over the board, I do not know if that was the ideal way to do it but that's the only way I know how to do it. Now, I got a ton of Package to Package spacing errors that I do not know how to get rid of. I understand that I can waive these errors and there's probably no consequences in doing that, But , where I work, they don't like that and I personally would rather learn how to prevent my Allegro 17.2 from flagging these , especially that I know that it is manufacturable. I have a feeling this can be done through the constraint manager but after playing with it for hours , I don't know what I am doing anymore and would love to get as detailed of tips as possible.
Here is a screenshot below to help visualize the problem:

Here are the errors after placing those Vias / Plated Through Holes (They're meant to be vias , but somehow only when I have the shapes filter selected is when Cadence detects them).
There were 0 errors before , so all the errors are package to package spacing errors that showed up afterwards.

Thank you all Very much.

Best regards.

Neil Mustafa.