Finding starting layer and routed layer of a signal via

It is possible to generate a via report by padstack category along with padstack names, start and end layers, and count of all vias. This can be done by using the following Extracta command file:

COMPOSITE_PAD
CLASS = VIA CLASS
NET_NAME
NET_NAME_SORT
PAD_STACK_NAME
PAD_STACK_CATEGORY
PAD_TYPE
VIA_X
VIA_Y
NET_VIA_COUNT
START_LAYER_NAME
END_LAYER_NAME
END

Save the above content in a text file (example, test.txt) and save this file in your current working directory.

Now, when you open the PCB Editor, you can see the test.txt file in your Reports dialog box (Tools > Report).

Hi John,

Thank you for the reply,

is it possible to find the via stub for all signal similarly?

Like, the the component placement is done in top layer and signal routing done in signal layer 1 
so, for that two through hole via used in the both source and destination and our requirement to find its stub length..

image for reference

Hi JITHINDEV, A stubs report is available in the quick reports menu (Tools >Quick Report >Backdrill Report). 

The reported "stub" is the total length of the backdrill up to the maximum depth to the conductor layer. 

To enable reporting for all vias or selective vias, assign the BACKDRILL_MAX_PTH_STUB property to the desired nets. This can be done using the Edit > Property command on selected nets in the Allegro PCB Editor or by using the General Properties worksheet in Constraint Manager.

Following an "Update Backdrill" operation, the quick report will reflect accurate backdrill information. For more in-depth information, you can opt to use the "Backdrill Setup and Analysis" tool in the Manufacture > NC menu. Use the Analyze button to display a detailed report. .

Internally we have recently discussed a useful feature called the ECL report. When we add the ECL property to a net(s) we can generate a report that looks as follows:

This shows the data path of the Net MEMORY.RA15 including the via lengths. 
“*” means it is one of the end point of the net. “T” means T-Junction.

NOTE: it does not generate report for hybrid signals (Traces + Power Plane) since there is limitation on calculating length shapes used for signal routing.

To do this please follow these steps:

Step 1) Add ECL Property to the Nets you want to examine.
Step 2) Save the design to a temporary database.
Step 3) From OS prompt type: report -v ecl <temp_design>.brd

You could also use EXTRACTA to generate a file that can be loaded into a spreadsheet.
Step 3) extracta <temp_design>.brd ecl_rep my_ecl_report.txt

It is best to remove ECL Property from Nets when you are finished, so it is recommended to save a temporary database as per Step 2 above.

What is ECL property & how do we define it ?