Unveiling the power of PCB Design for Manufacturing checks in Allegro X and OrCAD X

In the dynamic realm of PCB design and manufacturing, staying ahead with cutting-edge tools is paramount. OrCAD and Allegro PCB Editors offer a suite of powerful Design for Manufacturing (DFM) checks that are indispensable for engineers seeking fabrication and production reliability in their projects. OrCAD/Allegro tools provide a robust suite of Design Rule Checks that go far beyond basic spacing checks.  

The large range of extended checks are accessed in the Manufacturing worksheet of Constraint Manager in the Worksheet Selector pane, as shown below.

The special manufacturing checks are split into three sections:

1. Design for Fabrication (DFF) constraints are advanced constraints relating to the PCB layer fabrication including mask, copper, and silkscreens.
2. Design for Assembly (DFA) constraints relate to product’s advanced assembly failures such as package-type-specific spacings, package-to-PCB layer interactions, component lead checks, pastemask, and fiducial checks.
3. Design for Test (DFT) are fabrication and assembly checks that relate specifically to the testpoint placement and special considerations governing testpoints.

The expanded subset of checks within these groups is quite extensive. It is recommended that designers become familiar with these, which are detailed in your installation documentation viewer. The full list of checks can be accessed using the OrCAD/Allegro menu (Help > Documentation) and searching Design for Fabrication. Here, you will find an extensive list of fabrication checks listed in the navigator with descriptions of each check.

Designers can apply these DFM rules in a region-based setup to account for specialised circuit elements with exceptional requirements. For example, designers can set general default component spacing rules for the entire design and can create a region (or regions) in the design and then, apply any new set of spacing rules to each region.

Examples of useful advanced DFM constraints

Package - to - Package Spacing checks are used by many designers. This feature is managed by the DFA constraint spreadsheet, shown below as PkgToPkg Spacing. This lets designers organise symbols into specific classes by using the DFA_DEV_CLASS property with a DFA_Bound outline, which can be automatically applied to the symbol. These categorised symbols can then be spaced apart with distinct granular spacings beyond that of the basic placement rule. 

Via Under Component is found in the Design for Assembly > Spacing > Via under Component worksheet. This constraint defines the packages under which vias should not be present. A separate UI is launched to select those packages. Checking for traces under components is also available separately.

In addition, Through-hole pins under SMD component checks for any component through-pins positioned incorrectly beneath components on the opposite side of the board. In large hybrid designs, this can be difficult to find manually. Using this feature, DRC flags will be displayed indicating that the through-hole pins are violating another component’s space on the opposite side, hindering the placement. 

Etch text to Copper Shapes: Using an Allegro Venture or Enterprise Suite license, it is now possible to check Shape-to-Non-signal features such as etch text. This can be done using the Design for Fabrication > Copper Spacing worksheet. Create a new DFF CSet and enter a constraint value to apply the CSet rules against different layers, conductors, or planes.

Same net checks: These advanced checks can also be found in the Design for Fabrication > Copper Spacing worksheet. Care must be taken to enable these checks in the Analysis Modes window. These are not enabled by default. Various checks can be found here, which can be set independently for thru vias, Blind/Buried vias, or Micro vias.

Cline width vs. padstack width: Excessive trace widths connecting to pads can be checked using the “Maximum Line into pad ratio” for both SMD and through-pins. This is available under Copper Features within the Design for Fabrication constraints. This check uses a percentage constraint value to check the trace entry into the pad.

The features listed here are just a sample of the many checks available; these will enable an advanced granular control over your designs while providing you with a real-time DRC validation.

If you have any questions or comments about these or any other Manufacturing constraints, please leave a comment.