PCB allegro 17.4 CoB wirebond to die pin limitation =100

I am a PCB designer who got roped into packaging after we discovered you can't export ODB from HFSS and fabricate anything.  

3D visualization of wirebonds might be a reason to use the chip on board function in Allegro.  I set it up once.  Marketing loved it.  Engineers waiting for their designs, not so much.  Package design is a smaller scale than Allegro.  Grid resolution in the 10 micron range or something like that.  With SIP, the die stack manager is critical but not covered in SIP ILS training for some reason.

Since you have it available, I think an Allegro background makes APD easy to learn.  APD supports building a complete package model to extract SI and thermal models from.   Package designer had optimized everything in HFSS before I knew about the project.

Allegro designs don't use wirebonds often.  For RF packages, wirebond data comprised of a set of XY coordinates from the center of the substrate.   Haven't had anyone ask for detailed shapes of the individual wires.  

SIP/APD adds physical DRCs for spacing, angles of wirebonds, that Allegro doesn't offer.  If you design your package substrate in Allegro, could you enlist the help of the fabricator to validate wirebonds for yield?

Hi Robert,

thank you for your reply.
I understand your point of view, but we don't have the same needs....

I don't need to package a chip or design a substrate, I design a PCB to test a first chip prototype (currently in die version before packaging).
On this PCB I have some connectors, a level translator, LDO chips + the die.
As the quantity is small (2 boards), the size of the PCB is small (12x6 cm) and we have the machines in our workshop: we carry out the PCBA + wirebonding in-house.
the process is simple: we stick the die on the card and we wirebond the pin of the die to the PCB.
This is actually a chip on board (COB) project and I don't need to export any simulation models like in packaging process.
Today we program the wirebond machine manually (each connection 1 by 1) and use a workaround with a virtual copper layer to simulate wirebond in allegro...
I would just like to use allegro appropriately for COB design but the limitation of "100 die pins" discourages me...

so my questions remain:

-why this limitation is never mentionned in documentation?

-why this limitation exist  ? 

-I would like to know if anyone knows of a solution to get around this limitation.

-is this limation still there in next version of Allegro 22 or 23?

regards,

Seb

Hi Robert,

thank you for your reply.
I understand your point of view, but we don't have the same needs....

I don't need to package a chip or design a substrate, I design a PCB to test a first chip prototype (currently in die version before packaging).
On this PCB I have some connectors, a level translator, LDO chips + the die.
As the quantity is small (2 boards), the size of the PCB is small (12x6 cm) and we have the machines in our workshop: we carry out the PCBA + wirebonding in-house.
the process is simple: we stick the die on the card and we wirebond the pin of the die to the PCB.
This is actually a chip on board (COB) project and I don't need to export any simulation models like in packaging process.
Today we program the wirebond machine manually (each connection 1 by 1) and use a workaround with a virtual copper layer to simulate wirebond in allegro...
I would just like to use allegro appropriately for COB design but the limitation of "100 die pins" discourages me...

so my questions remain:

-why this limitation is never mentionned in documentation?

-why this limitation exist  ? 

-I would like to know if anyone knows of a solution to get around this limitation.

-is this limation still there in next version of Allegro 22 or 23?

regards,

Seb