Dynamic copper not voiding around vias and through-holes

Question

I am running into issues updating a layout. I am using Orcad PCB Designer 22.1 Standard license. 
 I am not able to generate dynamic shapes with proper voids around vias and through-holes. On some layers, it will autofill the voids and others it won't. 
 dbdoctor gives the following errors: 
 (---------------------------------------------------------------------) 
 ( ) 
 ( DBDOCTOR ) 
 ( ) 
 ( Drawing : 41-00058-01_REV02.brd ) 
 ( Software Version : 22.1S005 ) 
 ( Date/Time : Mon Apr 15 13:43:56 2024 ) 
 ( ) 
 (---------------------------------------------------------------------)

WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L2_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L4_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L5_SIG_H. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L6_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L7_VCC. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L8_VCC. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L9_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L10_SIG_H. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L11_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = T_N20_30 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L13_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L2_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L4_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L5_SIG_H. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L6_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L7_VCC. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L8_VCC. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L9_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L10_SIG_H. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L11_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: in PAD STACK padstack name = EX67Y67D47P 
 WARNING(SPMHDB-46): Illegal null pad. 
 No ANTI pad defined on layer L13_GND. 
 This could result in the wrong clearance on negative layer. 
 
 WARNING: The following vias/pins have connections on positive layers 
 using a padstack without a REGULAR pad defined. Your 
 artwork output may not be correct. 
 
 Pin/Via Padstack Layer Location 
 ------------------------------------------------------------------------- 
 D23.8 5CT_NULL BOTTOM ( 4040.00 -106.00 ) 
 D23.8 5CT_NULL BOTTOM ( 4040.00 -106.00 ) 
 D17.8 5CT_NULL BOTTOM ( 4195.00 -101.00 ) 
 D17.8 5CT_NULL BOTTOM ( 4195.00 -101.00 ) 
 D16.8 5CT_NULL BOTTOM ( 4345.00 -101.00 ) 
 D16.8 5CT_NULL BOTTOM ( 4345.00 -101.00 ) 
 D24.8 5CT_NULL BOTTOM ( 2790.00 -106.00 ) 
 D24.8 5CT_NULL BOTTOM ( 2790.00 -106.00 ) 
 D18.8 5CT_NULL BOTTOM ( 2945.00 -101.00 ) 
 D18.8 5CT_NULL BOTTOM ( 2945.00 -101.00 ) 
 D15.8 5CT_NULL BOTTOM ( 3095.00 -101.00 ) 
 D15.8 5CT_NULL BOTTOM ( 3095.00 -101.00 ) 
 D5.8 5CT_NULL BOTTOM ( 1695.00 -101.00 ) 
 D4.8 5CT_NULL BOTTOM ( 1845.00 -101.00 ) 
 D11.8 5CT_NULL BOTTOM ( 1540.00 -106.00 ) 
 D11.8 5CT_NULL BOTTOM ( 1540.00 -106.00 ) 
 D5.8 5CT_NULL BOTTOM ( 1695.00 -101.00 ) 
 D4.8 5CT_NULL BOTTOM ( 1845.00 -101.00 ) 
 D12.8 5CT_NULL BOTTOM ( 290.00 -106.00 ) 
 D3.8 5CT_NULL BOTTOM ( 595.00 -101.00 ) 
 D3.8 5CT_NULL BOTTOM ( 595.00 -101.00 ) 
 D6.8 5CT_NULL BOTTOM ( 445.00 -101.00 ) 
 D6.8 5CT_NULL BOTTOM ( 445.00 -101.00 ) 
 D12.8 5CT_NULL BOTTOM ( 290.00 -106.00 )

Regenerating DRC 
 Original DRC errors: 855 
 Updated DRC errors: 855 
 DRC elapsed time: 00:00:01 
 
 44 warnings, 0 errors detected, 0 errors fixed.

dsizzle83 · Accepted Answer

Thank you for your reply. I'm still not sure the root cause, but I found a workaround. My original design was done by a contractor using 17.2. I modified the cross-section on the original design and exported the constraints to the new design. After importing the constraints, I was able to update the shapes and get proper voids around vias.

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Dynamic copper not voiding around vias and through-holes

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