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How Should I Implement Vias in Pad?

John T

Having reviewed many PCBs for Manufacturability/Assembly, I wanted to highlight two mistakes that I keep seeing in designs regarding thermal vias in diepads. If you are familiar with this area, please feel free to add to the conversation, or to contradict, based on your experience. All thoughts, opinions, and questions are welcome.

 

For clarity, I am referring to vias placed within smd pads in order to improve the thermal performance of certain components.

There is plenty of information online explaining why these are used, but I don’t find much information explaining how to implement this.

 

Mistake 1 is regarding component placement. Normally, these via pads are completely exposed by the soldermask layers. The via pads themselves are not visibly distinguishable from the copper surface; only the array of holes are visible in the diepad. Therefore, the solder paste can flow freely down the holes during reflow.

This is not an issue as long as you have designed your PCB with DFM in mind. And we are talking about automated production, assuming no hand-soldering or rework is planned. To get all of your components to solder correctly the first time in an automated process, you should ensure that such surface components are placed on “reflow side 2” of the board. This ensures that any paste protruding through the via holes does not cause obstruction to the stencil on the second reflow side.

The reason is Gasketing: This is the seal that a stencil has with the surface when placed on the PCB. The thickness of the stencil normally dictates the volume of paste deposited for a given aperture. “Poor gasketing” is caused by protruding solder bumps, which elevate the stencil and place additional unwanted paste. As per the QFN image above, this can have detrimental effects on the small components placed on the opposite side. An unpredictable amount of paste will be deposited due to the elevation of the stencil, leading to a number of possible soldering defects such as shorts or tombstoning.

 

Mistake 2: Suppose you already have fully open vias, with soldermask openings that result in full exposure of the via pads on both the top &  bottom side. Opening these vias individually is not advised. Designers should instead create a larger exposed metal shape on the opposite side of the board. This in known as a wetting area.

 

 

This helps lower the profile of through-solder and reduce any potential effects that may occur because of too much solder accumulation down one hole. Solder accumulation patterns are random, as the solder flux boils and bubbles its way off the pad. It is best that an exposed copper surface is provided on the opposite side as a large wetting area. This will enable any solder flowing through to flow freer and flatter on the opposite side. This solder-management technique is best for the overall quality and reduction of solder balls.

 

So, which side is the first reflow side of your board? Do you know, and how do you decide?

There may be a lot more to discuss here, but for now, please consider the points presented above. Any further comments or opinions are welcome.  

Parents

  • Hi John,

    First thing the, sizing of the drill holes that act as the thermal vias is important. Over many designs I have never seen wicking of the solder go down the holes. I typically
    use either a 10 mil hole to 14mil hole. These holes are small so wicking does not occur.

    I don't place vias in the pad like in your picture. When creating the footprint I use the multi drill option and embed the holes directly into the physical padstack. Doing this means a footprint is ready to go, one doesn't have to worry about a designer forgetting to add the vias onto the pad. The other point here is while one can add vias in the
    pcb editor you also have to consider the net name of the via before placing the via on the pad and they must be the same to stop DRC hell.

    On the bottom side of the board if there is a ground plane and the physical thermal pad is also ground, I typically do a direct connect to the plane. When creating the footprint the pad on the top will exist on all layers since the multidrill is used.

    There are other considerations too. These days it is possible for the board house to do via vill or plugging of the holes as method to mitigate wicking. On small holes this
    is hard to do, larger holes it can be done but adds expense. One mistake I have noticed is that sometimes the holes on the bottom side of the board are covered with soldermask the idea to possibly avert wicking. Not a good idea because when the board goes through the IR process gasses can get produced in the hole and lead to blow out.

    On the reflow side, I couldn't care less lol. I had not had a cm come back and say they couldn't build the board. Certainly though we do consider this and make the design in such a way so that there is always margin and it can be manufactured.

    Here is a pic of the multi drill option I use. This particular one is for a RF Semiconductor and its solder pad in gnd.

    The multi drill option in Allegro is a very handy feature. It works great and can save alot of time !. I think the main consideration is the hole sizing and getting that correct.
    What size via holes did you use in your design example ?.

    All the best.

  • in reply to excellon1

    Hi Excellon1, so glad that you brought up the point about  gas blow out and air bubble trapping. I was hoping someone would discuss any of their experiences with this... 

    fyi the via size used in the the design above was 12mil. We would have witnessed some paste protrusion even at this size. I feel that solder type could have been a factor in this though. 

    Glad to hear you are making good use of the multi-drill array feature in Padstack Editor! The 10 mil spacing seems very tight. Our DFF experts used to panic over anything approaching <=15 mils. This was seemingly a general limitation of FR4 material strength; are you using polyimide or other here?

    Thanks for your insights! 

  • in reply to John T

    Hi John,

    Yes the 10mil spacing is very tight, Normally we would go with 20 mil spacing or larger. That particular picture was from an older
    design done for a special application. The material was an FR4 hybrid as I recall.
    It's interesting that you see paste protrusion on using 12mil holes. I can honestly say I have never seen that. If your calling out 12mil drill
    then after the plating process the hole will be slightly smaller. Even 12mil is a really really small hole Slight smile

    I Have had very good success with the multi drill feature in the padstack editor. Works great !. There are times when it cant be used if an odd
    footprint calls out a different thermal arrangement, in that case a standard via does the job.

    All the best.

Reply
  • in reply to John T

    Hi John,

    Yes the 10mil spacing is very tight, Normally we would go with 20 mil spacing or larger. That particular picture was from an older
    design done for a special application. The material was an FR4 hybrid as I recall.
    It's interesting that you see paste protrusion on using 12mil holes. I can honestly say I have never seen that. If your calling out 12mil drill
    then after the plating process the hole will be slightly smaller. Even 12mil is a really really small hole Slight smile

    I Have had very good success with the multi drill feature in the padstack editor. Works great !. There are times when it cant be used if an odd
    footprint calls out a different thermal arrangement, in that case a standard via does the job.

    All the best.

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