"derive connectivity" question

Hi Masa,

Could you please provide an update on the actions taken to address the file shrink issue? Additionally, it would be helpful if you could share a snapshot of the misalignment that occurred, as this will enable me to better understand the problem and provide more effective support.

me too, in package design, There is a difference in thermal expansion coefficient between silicon and substrate. so need to shrink the die bump location. the pin and the via will offset.  do you have solution for this case?

Do you found any solution for the offset between via and pin?

hello:

i used a different cam rool.

cadence allegro is not cam but cad.

regards

masa