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auto routing working time

JJ202503101021

Hi,

I am trying auto routing by smart route option but it is taking long time. Design file has too many vias, layers and shaps.

So, I'd like to know what is the most impacts to working time and it has setup option to reduce working time.

thanks,

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  • 0

    What auto-router are you talking about? which tool? which menu?

  • 0 in reply to Elecguy

    Hi. 

    The tool is PCB editor 17.4 and PCB router 17.4

    Route > PCB Router > Route Automatic.

    If you know the PCB Router tool, do you know which menu can make to limit Via holes? It already made Vias holes in layout.

    Thanks,

  • 0 in reply to JJ202503101021

    This is Cadence's implementation of the CCT (Cooper/Chyan) autorouter that they acquired in 1997.   

    I relied on it a bit too much from 1991.  Too many vias is always the result.  But, CCT was the first to follow daisy-chain ordering of pins, crosstalk spacing rules, etc.  There are settings to discourage it from throwing down vias (via tax?) but usually meant more manual cleanup.

    Siemens/Mentor Graphics acquisition of Intergraph VeriBest turned into Expedition.  This tool demonstrated better via management since 2004 using the Expedition router (with Boardstation) to finish a board that CCT couldn't get past 70% on (FPGA-based chip emulator with parallel busses routed between Xilinx Virtex-4 FPGAs with minimal stubs on 30,000 nets.) 

    SERDES, PCI-E, I2C and SPI bus have diminished the popularity of parallel busses outside of DDR memory implementations.   

    I could retire and never need a 24 layer stackup ever again.

    Today, Cadence Palladium systems are better solutions to emulate ASICs before tapeout.  Thank you Cadence. 

Reply
  • 0 in reply to JJ202503101021

    This is Cadence's implementation of the CCT (Cooper/Chyan) autorouter that they acquired in 1997.   

    I relied on it a bit too much from 1991.  Too many vias is always the result.  But, CCT was the first to follow daisy-chain ordering of pins, crosstalk spacing rules, etc.  There are settings to discourage it from throwing down vias (via tax?) but usually meant more manual cleanup.

    Siemens/Mentor Graphics acquisition of Intergraph VeriBest turned into Expedition.  This tool demonstrated better via management since 2004 using the Expedition router (with Boardstation) to finish a board that CCT couldn't get past 70% on (FPGA-based chip emulator with parallel busses routed between Xilinx Virtex-4 FPGAs with minimal stubs on 30,000 nets.) 

    SERDES, PCI-E, I2C and SPI bus have diminished the popularity of parallel busses outside of DDR memory implementations.   

    I could retire and never need a 24 layer stackup ever again.

    Today, Cadence Palladium systems are better solutions to emulate ASICs before tapeout.  Thank you Cadence. 

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