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Variable trace width during serpentine routing for PCIe 5.0 (PCB Editor 23.1)

bengelJF

Our electrical team was discussing the recommendation below from Texas Instrument's app note "High-Speed Layout for PCIe Gen 5":

It's easy enough to change the width of a given cline segment by hand, but ideally this would happen automatically during delay tuning so we don't have to do this by hand (takes more time, easy to miss a segment). Additionally, we run into the "snowman problem" when just changing trace widths, where the larger segment doesn't blend nicely into the smaller segment:

So, our question is this: In PCB Editor 23.1, is it possible to set up trace widths to adjust automatically to match TI's suggestion in their app note, and if so, is it further possible to get nice blended transitions from thinner to wider segments?

Thanks all!

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  • DavidJHutchins
    0

    I developed some skill code for this issue years ago, the solution for the 'snowman' issue was to split the 45' segment as the location of the width change, as show below:

  • masamasa
    0 in reply to DavidJHutchins

    hello david

     

    i have never worked on pcie but it looks like u can just add a taper at the width change to avoid the snowman issue.

     

     

    regards

    masa

Reply
  • masamasa
    0 in reply to DavidJHutchins

    hello david

     

    i have never worked on pcie but it looks like u can just add a taper at the width change to avoid the snowman issue.

     

     

    regards

    masa

Children
  • DavidJHutchins
    0 in reply to masamasa

    Hello Masa,

    the trace width difference between the inner pair & outer pair is not as large as you showed

    The Signal Integrity engineers at HP & Intel were happy with my solution...

  • avant
    0 in reply to DavidJHutchins

    Can someone clarify what this is trying to say?

    "As trace width increases, impedance drops.
    To compensate for the drop in impedance, increase trace width."

    thanks

  • DavidJHutchins
    0 in reply to avant

    As the spacing between the diff pair trace segments increase, the trace width need to increase to maintain the same impedance

  • avant
    0 in reply to DavidJHutchins

    Thanks, that's what I thought.

    They should rewrite or delete those two sentences. It made me question basic impedance practices.

  • masamasa
    0 in reply to DavidJHutchins

    hello david:

     

    i see the guideline saying ">3xW."

     

    so it can be 10xW if u have enough space.

     

    i think my design does not violate the guideline.

     

    maybe i do not know much about pcie.

     

    regards

    masa

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