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Variable trace width during serpentine routing for PCIe 5.0 (PCB Editor 23.1)

bengelJF

Our electrical team was discussing the recommendation below from Texas Instrument's app note "High-Speed Layout for PCIe Gen 5":

It's easy enough to change the width of a given cline segment by hand, but ideally this would happen automatically during delay tuning so we don't have to do this by hand (takes more time, easy to miss a segment). Additionally, we run into the "snowman problem" when just changing trace widths, where the larger segment doesn't blend nicely into the smaller segment:

So, our question is this: In PCB Editor 23.1, is it possible to set up trace widths to adjust automatically to match TI's suggestion in their app note, and if so, is it further possible to get nice blended transitions from thinner to wider segments?

Thanks all!

  • avant
    0 in reply to DavidJHutchins

    Thanks, that's what I thought.

    They should rewrite or delete those two sentences. It made me question basic impedance practices.

  • masamasa
    0 in reply to DavidJHutchins

    hello david:

     

    i see the guideline saying ">3xW."

     

    so it can be 10xW if u have enough space.

     

    i think my design does not violate the guideline.

     

    maybe i do not know much about pcie.

     

    regards

    masa

  • DavidJHutchins
    0 in reply to masamasa

    Masa,

    I was told that you need to change the width on both segments in the section where the distance is larger,

    in the image you can see both are changed...

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