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  3. How to Generate Parasitic Reports for All Nets in Allegro...

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How to Generate Parasitic Reports for All Nets in Allegro PCB Editor, and How Are They Calculated?

Electro Node
Electro Node 2 months ago

Hi Folks,

 

Hello I would like to generate parasitic reports (resistance, capacitance, and inductance) for all nets in my Allegro PCB Editor design. Can someone explain the recommended method or workflow to generate these reports from board files?

Additionally, I’m interested in understanding how Allegro calculates these parasitic values. What design parameters (trace geometry, stack‑up, materials, vias, etc.) are considered, and whether the calculations are based on field solvers or rule‑based models.

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  • excellon1
    +1 excellon1 2 months ago

    Hi,

    Here is a report file to try & run. This report file is based on a 2lyr Board, the bottom layer is a "plane Layer" in the Xsection & the top layer is the etch conductor.

    save the following as a .txt file and load it into the report editor.

    NET
    NET_NAME
    NET_NAME_SORT
    NET_CAPACITANCE
    NET_RESISTANCE
    NET_INDUCTANCE
    NET_IMPEDANCE_AVERAGE
    NET_IMPEDANCE_MINIMUM
    NET_IMPEDANCE_MAXIMUM
    NET_ETCH_LENGTH
    END

    Allegro uses a solver to do calculations, however for meaningful impedance calculations you need to specify a "Plane Layer" in the cross section editor. The editor uses the plane layer which is treated as a reference plane to do the calculations. A use case would be something like a 50 ohm microstrip line etc.

    For general impedance calculations / Board Analysis of a graphical nature, it is easier to use the built in "Analysis Work Flows" On the tool bar look for the "Analyze" menu item.

    Best Regards.

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  • excellon1
    +1 excellon1 2 months ago

    Hi,

    Here is a report file to try & run. This report file is based on a 2lyr Board, the bottom layer is a "plane Layer" in the Xsection & the top layer is the etch conductor.

    save the following as a .txt file and load it into the report editor.

    NET
    NET_NAME
    NET_NAME_SORT
    NET_CAPACITANCE
    NET_RESISTANCE
    NET_INDUCTANCE
    NET_IMPEDANCE_AVERAGE
    NET_IMPEDANCE_MINIMUM
    NET_IMPEDANCE_MAXIMUM
    NET_ETCH_LENGTH
    END

    Allegro uses a solver to do calculations, however for meaningful impedance calculations you need to specify a "Plane Layer" in the cross section editor. The editor uses the plane layer which is treated as a reference plane to do the calculations. A use case would be something like a 50 ohm microstrip line etc.

    For general impedance calculations / Board Analysis of a graphical nature, it is easier to use the built in "Analysis Work Flows" On the tool bar look for the "Analyze" menu item.

    Best Regards.

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  • Electro Node
    0 Electro Node 2 months ago in reply to excellon1

    Hi,

    Thank you for sharing the report template, this is very helpful. I tested it on one of my designs and was able to successfully generate NET‑level R, L, and C values.

    I have a follow‑up question for deeper understanding:

    1. How does Allegro handle parasitic extraction for multilayer boards where multiple reference planes exist (e.g., stripline vs microstrip)?
    2. Are via contributions (via barrels, stubs, antipads) included in the NET_INDUCTANCE and NET_CAPACITANCE calculations by default?


    Any clarification or documentation references on solver assumptions would be greatly appreciated.

    Many thanks for the previous response it is greatly appreciated. 

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  • excellon1
    0 excellon1 2 months ago in reply to Electro Node

    Hi Electro.

    Very good questions. So the reports are generated based on the cross section, not the physical board as far as I can see here.
    The issue is the assumption of an infinite reference plane. For example. Assume you have a microstrip of say 50 Ohms in your design. You can easily calculate this with a close approximation in the cross section editor by plugging in the width of the trace, however on your physical board that means your going to have a ground plane below that microstrip.If you forget or remove the ground plane on the board and run the report you will see that it still reports 50 ohms for your microstrip. Clearly in the real world this will not be the case when the board is made. 

    From V17.2 of Orcad/Allegro on-wards, Cadence included a very useful subset of the "Sigrity Analysis Tools" within the PCB Editor.
    Sigrity would be their SI tool. In Orcad/Allegro on the tool-bar look for the Analyze Menu to access them.

    Anyway the tool models the actual board to determine impedance, capacitance etc. You can include any Net or all of them etc so it has good flexibility. Ideally you would want to use this as opposed to just running a report that is based on the static cross section.
     

    I don't have any details of what is going on under the hood, so if anything is unclear maybe reach out to your local Cadence rep for more clarity on that.


    Best Regards.

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  • Electro Node
    0 Electro Node 2 months ago in reply to excellon1

    Hi excellon1,


    Thank you so much for the detailed explanation. I now have much better clarity on this.


    Best regards,

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