How are you creating your testpoints?

It depend on testpoint usage destination.Of course, all are free of soldermask

Testpoint for debug/measurement:

- Added in schematic as components so it will have a refdes and appear on assembly drawing and silkscreen if available

- Will be either a smd pad or thru pad. Were thru pad in old time; now pretty all are smd pad

- Placed on the accessible layer. Generaly TOP

Testpoint for bend of nails or flying probe:

- Not in schematic

- will use either thru pin, thru via or undrilled via. Testpoints placed on schematic for debugging purpose may aslo be used 

- Ideally only on one face; can be both side on some case

- big enougth for nails

- distance between nails controled

- distance to components body controled

- 

- One by net by default

- Unconnected/unused pind have also testpoint by default

- May have several one on some case (verry smal component value, small tolerance value, higth current, ...)

- Personnaly i add these tespoint while routing, not at the end. May lead to heavy rework/modifications and/or impossiblity at the end of project. May have to revalidate routing on some case if added after routing completion. Testability IS a part of routing.

Don’t think probing more than 10-20% of nets is cost effective.  Most SMT errors are caught by AOI/xray. 

We drive probe placement from the schematic to verify we didn’t drop a MOSI signal (again) and it helps us reuse our test investment on future configurations.  Time-to-test will cause conversations you don’t want to have with an annoyed operations/finance team.  Our test fixtures are about $10K each.   It’s an expensive bottleneck to address if you need six of them running in parallel as loading firmware takes forever..

Things on our checklist:

Always have extra system ground probes near signal probes.  But, everyone likes fewer probes to get damaged/bent and don't understand grounding.   You can no-load that probe later.   Should you have ESD protection on your test probes?  Keep reading.

Basics of test:  turn on the DUT.  Verify power rails.  Measure current at the main input.  Make sure probes and fixture can supply enough power to program everything.  Verify power-on-reset/watchdog circuits.  Have hooks to program and communicate everything.  It’s pre-programmed on tape-and-reel before SMT until its no longer available.

With multiple ARM SOCs on the same board, we discovered why we shouldn’t multiplex the UART lines for test.  The ICs most susceptible to ESD failures is the DPDT switch on the UART lines controlled by the test system.  But, having every debug UART accessible supports remote debugging when things stopped working at an overseas production line. 

Lastly, ODMs love robust and portable test fixtures that can be moved around the factory floor and still work.

Hi John,

Typically I go with options 1, 3 & 4

Option 1 is usually for only a few dedicated test points that it makes sense to have driven by the schematic.
Option 3, is kind of a norm in that all vias are left open, usually plated with ENIG.
Option 4, I use alot. For Communications equipment aka RF based that contain mostly mini and large planes I use a simple circle shape drawn in on the solder mask layer. Works well, Fast to do.

Bed of nails are less common today for ICT due to the cost, but for industrial high reliability boards & customer may what it. They don't care about the cost , In that regard the Allegro Route Editor "Specctra" has a highly capable Testpont generation option. Works very well !!

Best regards.