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  3. forcing separate clines

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forcing separate clines

archive
archive over 17 years ago

Allegro keeps all the segments (line/arc objects) that make up a cline (path object) in nice neat tail->head order in a list.

If you lay down a trace from a pin halfway to another pin then end your Connect command that leaves a stub cline with a ratsnest line to the destination pin. If you start a new Connect command, click on the end of the stub and complete the trace and end your command you get ONE cline from pin to pin - Allegro helps you by merging the two separate clines into one.

99% of the time this is what you'd want. But of course I need that 1% :

how can one prevent this behavior? To wit: how can one force Allegro to keep clines distinct?

pinA--------------------X-----------------------pinB

instead of merging to get

pinA--------------------------------------------pinB


TIA,

Chris Walters
local Cadence guru
()


Originally posted in cdnusers.org by kerchunk
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  • archive
    archive over 17 years ago

    Here's couple of methods:
    1) Logic->Net Schedule and add a "T point" (Rat T).
    2) Route the first part of the cline and FIX the cline. Then route it the rest of the way.


    Originally posted in cdnusers.org by Randy R.
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  • archive
    archive over 17 years ago

    Thx for the tips! It doesn't look like a rat_T object can be algorithmically placed on the end of a cline/clineseg object ( or can it?)
    I can use the 2nd method for now.

    Thanks again!


    Chris Walters
    local Cadence guru
    ()


    Originally posted in cdnusers.org by kerchunk
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  • archive
    archive over 17 years ago

    Not sure what you mean by algorithmically, but you can set a constraint using it. For example, in the Min/Max Propagation Delay section (or anywhere you can create a pin-pair) you can right-click on the netname, create a pin pair, and select the T-point as one of the pins.


    Originally posted in cdnusers.org by Randy R.
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  • archive
    archive over 17 years ago

    In A16 i don't know what its called, but in A15.5.1 one could create a symbol under the logic menu (eg add a 0201). One of the clines need a new netname to aviod drc and xnet errors.
    Other methods can be used, but will create either a missing connection or drc error.
    Sincerely


    Originally posted in cdnusers.org by Malmir
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  • redwire
    redwire over 17 years ago

    There's a really simple way to do this.

    Let's say your line is 8.5 mils wide.  Assume database accuracy is set to 3...

    Next select edit->change (find filter = clines); Set line width to 8.501

    RMB->Cut

    Click where you want. move over 1 mi. Click

    Now you have a segment with a different line width (in Allegro's database) but it won't actually  change anything in the fabrication world.  The tolerance on fabrication is in the neighborhood of 0.5 mils.

     

    Just another way to address the problem.

    HTH 

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